After two decades of intensive development, 3-D integration has proven invaluable for
allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink …

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for
achieving high-density integration, high-speed connectivity, and for downsizing of electronic …

As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer
bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias …

Understanding the relevant permeability properties of ultrafiltration membranes is facilitated
by using materials and procedures that allow a high degree of control on morphology and …

In this work, e-beam lithography patterns have been specifically designed and fabricated
which provide the opportunity to probe the collapse behavior of both positive and negative …

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the
advances in integrated circuit fabrication process and the market demands for devices with …

Planar radio-frequency (RF) on-chip inductors suffer from large electromagnetic losses,
stemming from the low resistivity silicon substrate. Though it is well-known that 3 …

An edge-free structure and hermetic encapsulation technique are presented that enable SiO
x-based resistive random-access memory (RRAM) operation in air. A controlled etch study …

In this paper, a pressurization method for manufacturing an independent impulsion system is
proposed. The method consists in inserting a deformable material filling a microchamber …

Manufacturing semiconductor technologies in production facilities typically involves
performing hundreds to thousands of steps in pipelines that can include hundreds of …