M Wedler, D Stoffel, R Brinkmann… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
We propose a normalization technique for verifying arithmetic circuits in a bounded model- checking environment. Our technique operates on the arithmetic bit-level (ABL) description …
T Achterberg, R Brinkmann, M Wedler - 2007 - opus4.kobv.de
We address the property checking problem for SoC design verification at the register transfer level (RTL) by integrating techniques from integer programming, constraint programming …
Abstract The Satisfiability Modulo Theories (SMT) problem is a decision problem for the satisfiability of first-order formulas with background theories. In the last few years, decision …