In modern large-scale, high-speed digital integrated circuit (IC) design, power consumption
of the clock network usually dominates the dynamic power of the chip due to its highest …

Clock gating is a predominant technique used for power saving. It is observed that the
commonly used synthesis-based gating still leaves a large amount of redundant clock …

We propose a power-driven flip-flop merging and relocation approach that can be applied
after conventional timing-driven placement and before clock network synthesis. It targets to …

Clock power is the major contributor to dynamic power for modern integrated circuit design.
A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to …

Placement is considered a fundamental physical design problem in electronic design
automation. It has been around so long that it is commonly viewed as a solved problem …

Optimization for power is always one of the most important design objectives in modern
nanometer integrated circuit design. Recent studies have shown the effectiveness of …

In this article, we propose a flip-flop merging algorithm based on agglomerative clustering.
Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm …

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has
been becoming a promising lower-power design technique. Many previous works tried to …

Flip-flops are the most common form of sequencing elements; however, they have a
significantly higher sequencing overhead than latches in terms of delay, power, and area …

Circuit clustering is usually done through discrete optimizations, with the purpose of circuit
size reduction or design-specific cluster formation. Specifically, we are interested in the multi …