Formal verification of high-level synthesis

Y Herklotz, JD Pollard, N Ramanathan… - Proceedings of the ACM …, 2021 - dl.acm.org
High-level synthesis (HLS), which refers to the automatic compilation of software into
hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific …

BLAST: Belling the black-hat high-level synthesis tool

M Abderehman, R Gupta… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
A hardware Trojan (HT) is a malicious modification of the design done by a rogue employee
or a malicious foundry to leak secret information, create a backdoor for attackers, alter …

Verification of scheduling of conditional behaviors in high-level synthesis

R Chouksey, C Karfa - IEEE Transactions on Very Large Scale …, 2020 - ieeexplore.ieee.org
High-level synthesis (HLS) technique translates the behaviors written in high-level
languages like C/C++ into register transfer level (RTL) design. Due to its complexity, proving …

[PDF][PDF] High-level synthesis tools should be proven correct

Y Herklotz, J Wickerson - Workshop on Languages, Tools …, 2021 - johnwickerson.github.io
With hardware designs becoming ever more complex, and demand for custom accelerators
ever growing, high-level synthesis (HLS) is increasingly being relied upon. However, HLS is …

[PDF][PDF] SoC 高级综合验证研究进展

胡健, 胡永扬, 王观武, 陈桂林, 杨海涛, 康云… - 计算机辅助设计与图形学 …, 2021 - jcad.cn
针对近年来片上系统(system on chip, SoC) 高级综合验证领域的工作, 首先分析了高级综合验证
的难点, 然后根据应用领域将算法分为3 类: 高级综合前端验证算法, 高级综合调度验证算法和 …

Formal verification of optimizing transformations during high-level synthesis

R Chouksey, C Karfa, P Bhaduri - Proceedings of the 12th Innovations in …, 2019 - dl.acm.org
Translation validation is the process of proving that the target code is a correct translation of
the source program being compiled. In this work, we propose a translation validation method …

[PDF][PDF] Towards an Approach for Translation Validation of Thread-level Parallelizing Transformations using Colored Petri Nets.

R Mittal, R Banerjee, D Blouin, S Bandyopadhyay - ICSOFT, 2021 - scitepress.org
Software applications often require the transformation of an input source program into a
translated one for optimization. In this process, preserving the semantics across the …

Counter‐example generation procedure for path‐based equivalence checkers

R Chouksey, C Karfa, K Banerjee, PK Kalita… - IET …, 2019 - Wiley Online Library
Path‐based equivalence checkers (PBECs) have been successfully applied for verification
of programmes from diverse domains and from various stages of high‐level synthesis. In the …

Improving performance of a path-based equivalence checker using counter-examples

R Chouksey, C Karfa, P Bhaduri - 2019 32nd International …, 2019 - ieeexplore.ieee.org
Path-based equivalence checkers (PBECs) have been successfully applied for verification
of programs from diverse domains and at various stages of high-level synthesis. These …

PNPEq: Verification of Scheduled Conditional Behavior in Embedded Software using Petri Nets

R Mittal, D Blouin… - 2021 28th Asia-Pacific …, 2021 - ieeexplore.ieee.org
Software for embedded systems goes through a scheduling phase where it is subjected to
optimizing transformations. In such a scenario, validating the preservation of semantics …