Haswell: The fourth-generation intel core processor
P Hammarlund, AJ Martinez, AA Bajwa, DL Hill… - IEEE micro, 2014 - ieeexplore.ieee.org
Haswell, Intel's fourth-generation core processor architecture, delivers a range of client
parts, a converged core for the client and server, and technologies used across many …
parts, a converged core for the client and server, and technologies used across many …
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology
CMOS technology scaling continues to drive higher levels of integration in VLSI design,
which adds more compute engines on a die. To meet the overall performance-scaling …
which adds more compute engines on a die. To meet the overall performance-scaling …
A 1 gb 2 ghz 128 gb/s bandwidth embedded dram in 22 nm tri-gate cmos technology
An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate
high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed …
high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed …
Tunnel FET negative-differential-resistance based 1T1C refresh-free-DRAM, 2T1C SRAM and 3T1C CAM
N Gupta, A Makosiej, H Shrimali… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
A refresh free and scalable ultimate DRAM (uDRAM) with 1T1C bitcell is introduced in this
paper. The memory uses the Negative Differential Resistance (NDR) property of Tunnel …
paper. The memory uses the Negative Differential Resistance (NDR) property of Tunnel …
Preventing reverse engineering using threshold voltage defined multi-input camouflaged gates
Semiconductor devices are increasingly getting more vulnerable to counterfeiting due to
Reverse Engineering (RE) of Intellectual Property (IP). Securing the IPs from counterfeiting …
Reverse Engineering (RE) of Intellectual Property (IP). Securing the IPs from counterfeiting …
Tunnel FET based ultra-low-leakage compact 2T1C SRAM
N Gupta, A Makosiej, A Vladimirescu… - … on Quality Electronic …, 2017 - ieeexplore.ieee.org
In this paper, an ultra-low-leakage 2T1C compact SRAM is proposed using Tunnel FETs
(TFETs). Proposed design utilizes negative differential resistance property of TFETs and …
(TFETs). Proposed design utilizes negative differential resistance property of TFETs and …
[图书][B] TFET integrated circuits: from perspective towards reality
This book describes the physical operation of the Tunnel Field-effect Transistor (TFET) and
circuits built with this device. Whereas the majority of publications on TFETs describe in …
circuits built with this device. Whereas the majority of publications on TFETs describe in …
Threshold-defined logic and interconnect for protection against reverse engineering
Securing the intellectual property (IP) from counterfeiting is an important goal toward
trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an …
trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an …
Modeling of retention time for high-speed embedded dynamic random access memories
S Ghosh - IEEE Transactions on Circuits and Systems I …, 2014 - ieeexplore.ieee.org
Embedded dynamic random access memory (eDRAM) is becoming a popular choice for
large cache applications due to its density, speed, and power benefits. One of the crucial …
large cache applications due to its density, speed, and power benefits. One of the crucial …
Design of almost-nonvolatile embedded DRAM using nanoelectromechanical relay devices
This paper proposes low-power design of embedded dynamic random-access memory
(eDRAM) using emerging nanoelectromechanical (NEM) relay devices. The motivation of …
(eDRAM) using emerging nanoelectromechanical (NEM) relay devices. The motivation of …