We determine the exact power of two-prover interactive proof systems introduced by Ben-Or,
Goldwasser, Kilian, and Wigderson (1988). In this system, two all-powerful …

Your road map for meeting today's digital testing challenges Today, digital logic devices are
common in products that impact public safety, including applications in transportation and …

We develop an exact algorithm for selecting flip-flops in partial scan designs to break all
feedback cycles. The main ideas that allow us to solve this hard problem exactly for large …

Increased levels of chip integration combined with physical limitations of heat removal
devices, cooling mechanisms and battery capacity, have established energy-efficiency as an …

We present the first complete translation of XPath into an algebra, paving the way for a
comprehensive, state-of-the-art XPath (and later on, XQuery) compiler based on algebraic …

As more low power devices are needed for applications such as IOT, reducing power and
area is becoming more critical. Reducing power consumption and area caused by using full …

Testing systems-on-a-chip involves applying huge amounts of test data, which is stored in
the tester memory and then transferred to the circuit under test during test application …

This paper presents a technique to enhance the testability of sequential circuits by
repositioning registers. A novel retiming for testability technique is proposed that reduces …

In this paper, we present a new method for selecting flip-flops for partial scan. Our method
ranks all flip-flops in a circuit based on a sensitivity analysis which estimates the relative …

This paper presents a non-scan design-for-testability technique applicable to register-
transfer (RT) level data path circuits, which are usually very hard-to-test due to the presence …