InGaAs gate-all-around nanowire devices on 300mm Si substrates

N Waldron, C Merckling, L Teugels… - IEEE Electron …, 2014 - ieeexplore.ieee.org
In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated
on 300mm Si substrates. For an LG of 60 nm an extrinsic gm of 1030 μS/μm at V ds= 0.5 V is …

Steep switching Si nanowire p-FETs with dopant segregated silicide source/drain at cryogenic temperature

Y Han, J Sun, B Richstein, F Allibert… - IEEE Electron …, 2022 - ieeexplore.ieee.org
Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW
diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 …

Steep Subthreshold Swing n- and p-Channel Operation of Bendable Feedback Field-Effect Transistors with p+–i–n+ Nanowires by Dual-Top-Gate Voltage …

Y Jeon, M Kim, D Lim, S Kim - Nano letters, 2015 - ACS Publications
In this study, we present the steep switching characteristics of bendable feedback field-effect
transistors (FBFETs) consisting of p+–i–n+ Si nanowires (NWs) and dual-top-gate structures …

Interface traps in InAs nanowire tunnel FETs and MOSFETs—Part II: Comparative analysis and trap-induced variability

D Esseni, MG Pala - IEEE transactions on electron devices, 2013 - ieeexplore.ieee.org
This paper extends the analysis of the companion paper by presenting a comparative
analysis of the impact of interface traps on the IV characteristics of InAs nanowire tunnel …

Gate all around MOSFET with vacuum gate dielectric for improved hot carrier reliability and RF performance

R Gautam, M Saxena, RS Gupta… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
In this paper, gate all around (GAA) MOSFET with vacuum gate dielectric is proposed for the
first time for improved hot carrier reliability and RF performance. Analog and RF …

Self-curable gate-all-around MOSFETs using electrical annealing to repair degradation induced from hot-carrier injection

JY Park, DI Moon, ML Seol, CK Kim… - … on Electron Devices, 2016 - ieeexplore.ieee.org
Device degradation induced by hot-carrier injection was repaired by electrical annealing
using Joule heat through a built-in heater in a gate. The concentrated high temperature …

Charge-based modeling of double-gate and nanowire junctionless FETs including interface-trapped charges

A Yesayan, F Jazaeri, JM Sallese - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Nanowire (NW) semiconductors are interesting devices for being used as sensors. Such
NWs are doped silicon channels with electrical contacts at both ends, which is a kind of the …

A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers

R Shankar, G Kaushal, S Maheshwaram… - … on Device and …, 2014 - ieeexplore.ieee.org
The reliability of multigate metal-oxide-semiconductor (MOS) devices is an important issue
for novel nanoscale complementary MOS (CMOS) technologies. We present an analytic …

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

Y Yang, YS Park, J Son, K Cho, S Kim - Scientific reports, 2021 - nature.com
In this study, we examine the electrical characteristics of silicon nanowire feedback field-
effect transistors (FBFETs) with interface trap charges between the channel and gate oxide …

Replacement fin processing for III–V on Si: From FinFets to nanowires

N Waldron, C Merckling, L Teugels, P Ong… - Solid-State …, 2016 - Elsevier
In this paper we review the details and results of the replacement fin process technique used
to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled …