Signal integrity design for high-speed digital circuits: Progress and directions
This paper reviews recent progress and future directions of signal integrity design for high-
speed digital circuits, focusing on four areas: signal propagation on transmission lines …
speed digital circuits, focusing on four areas: signal propagation on transmission lines …
Energy-efficient 5G phased arrays incorporating vertically polarized endfire planar folded slot antenna for mmWave mobile terminals
J Park, H Seong, YN Whang… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
An energy-efficient 5G phased array incorporating a novel vertically polarized (V-pol) endfire
planar folded slot antenna (PFSA) for user devices (TIE) is presented. First, we analytically …
planar folded slot antenna (PFSA) for user devices (TIE) is presented. First, we analytically …
Organic packages with embedded phased-array antennas for 60-GHz wireless chipsets
DG Kam, D Liu, A Natarajan… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
A multilayer organic package with embedded 60-GHz antennas and fully integrated with a
60-GHz phased-array transmitter or receiver chip is demonstrated. The package includes …
60-GHz phased-array transmitter or receiver chip is demonstrated. The package includes …
Is 25 Gb/s on-board signaling viable?
What package improvements are required for dense, high-aggregate bandwidth buses
running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on …
running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on …
A 16-Gb/s 14.7-mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16/256-QAM and channel response detection
A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and
high-order digital signal modulations is presented for serial link applications. The TX …
high-order digital signal modulations is presented for serial link applications. The TX …
A Fully Integrated 0.13-m CMOS 40-Gb/s Serial Link Transceiver
A fully integrated 40-Gb/s transceiver fabricated in a 0.13-mum CMOS technology is
presented. The receiver operates at a 20-GHz clock performing half-rate clock and data …
presented. The receiver operates at a 20-GHz clock performing half-rate clock and data …
A K-Band Low-Power Colpitts VCO With Voltage-to-Current Positive-Feedback Network in 0.18 CMOS
TP Wang - IEEE Microwave and Wireless Components Letters, 2011 - ieeexplore.ieee.org
A circuit topology suitable for low-power Colpitts voltage-controlled oscillators (VCOs) is
presented in this letter. By employing the proposed voltage-to-current positive-feedback …
presented in this letter. By employing the proposed voltage-to-current positive-feedback …
Low-cost antenna-in-package solutions for 60-GHz phased-array systems
DG Kam, D Liu, A Natarajan… - 19th Topical Meeting …, 2010 - ieeexplore.ieee.org
A low-cost, fully-integrated antenna-in-package solution for 60-GHz phased-array system is
demonstrated. Sixteen patch antennas are integrated into a 28 mm× 28 mm ball grid array …
demonstrated. Sixteen patch antennas are integrated into a 28 mm× 28 mm ball grid array …
Signal/power integrity modeling of high-speed memory modules using chip-package-board coanalysis
HH Chuang, WD Guo, YH Lin, HS Chen… - IEEE transactions on …, 2010 - ieeexplore.ieee.org
Under the platform of a high-speed double-data-rate three (DDR3) memory module, a
modeling method considering all the significant effects from the chip, package, and board …
modeling method considering all the significant effects from the chip, package, and board …
Fast and accurate frequency-dependent behavioral model of bonding wires
TP Wang, YF Lu - IEEE Transactions on Industrial Informatics, 2017 - ieeexplore.ieee.org
A proposed model of bonding wires is presented in this paper. For a regular double-π
bonding-wire model considering the skin effect, nine parameters should be determined …
bonding-wire model considering the skin effect, nine parameters should be determined …