Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance
S Banerjee, D Chidambarrao, JA Culp… - US Patent …, 2012 - Google Patents
A method for implementing systematic, variation-aware integrated circuit extraction includes
inputting a set of processing conditions to a plurality of variation models, each model …
inputting a set of processing conditions to a plurality of variation models, each model …
Identifying parasitic diode (s) in an integrated circuit physical design
DW Kemerer, EW Seibert, LL Wang - US Patent 8,191,030, 2012 - Google Patents
In a first aspect of the invention, a method comprises trac ing terminals of a junction through
a circuit layout to associ ated power supplies to determine their respective defined bias …
a circuit layout to associ ated power supplies to determine their respective defined bias …
Wiring graphic verification method, program and apparatus
C Kodama, A Yoshitake - US Patent 7,120,881, 2006 - Google Patents
An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring
edges from overall wiring graphics, and a wiring width classification unit executes a Scaling …
edges from overall wiring graphics, and a wiring width classification unit executes a Scaling …
Identifying parasitic diode (s) in an integrated circuit physical design
DW Kemerer, EW Seibert, LL Wang - US Patent 7,490,303, 2009 - Google Patents
In a first aspect of the invention, a method comprises trac ing terminals of a junction through
a circuit layout to associ ated power supplies to determine their respective defined bias …
a circuit layout to associ ated power supplies to determine their respective defined bias …
Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance
S Banerjee, D Chidambarrao, JA Culp… - US Patent …, 2013 - Google Patents
“Design Rule Optimization of Regular Layout for Leakage Reduc tion in Nanoscale Design”
by Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao, IEEE (a 2008.* CS …
by Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao, IEEE (a 2008.* CS …
Identifying parasitic diode (s) in an integrated circuit physical design
DW Kemerer, EW Seibert, LL Wang - US Patent 8,756,554, 2014 - Google Patents
(57) ABSTRACT A method comprises tracing a first and second terminal of a junction
through a circuit layout to associated power Supplies to determine their respective defined …
through a circuit layout to associated power Supplies to determine their respective defined …
System and method for electrically and spatially aware parasitic extraction
A Bouamama, R Mitra, J Wang - US Patent 10,635,848, 2020 - Google Patents
The present disclosure relates to a computer-implemented method for parasitic extraction.
The method may include providing, using one or more processors, an electronic design …
The method may include providing, using one or more processors, an electronic design …
Detection method for identifying unintentionally forward-biased diode devices in an integrated circuit device design
AE Baizley, JA Iadanza - US Patent 7,685,548, 2010 - Google Patents
BACKGROUND High performance integrated circuit (IC) devices include processing
capabilities that require complex IC designs. While a high-level schematic of the IC device …
capabilities that require complex IC designs. While a high-level schematic of the IC device …
Method and arrangement for extracting capacitance in integrated circuits having non manhattan wiring
S Teig, A Chatterjee - US Patent 7,086,021, 2006 - Google Patents
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6,446,027 B1 9, 2002 O'Keefe et al. 6,526,549 B1 2, 2003 You 6,543,035 B1 4/2003 Ohba et …
6,446,027 B1 9, 2002 O'Keefe et al. 6,526,549 B1 2, 2003 You 6,543,035 B1 4/2003 Ohba et …