Computing in the dark silicon era: Current trends and research challenges
M Shafique, S Garg - IEEE Design & Test, 2016 - ieeexplore.ieee.org
Computing in the Dark Silicon Era: Current Trends and Research Challenges Page 1 2168-2356
(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE …
(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE …
The EDA challenges in the dark silicon era: Temperature, reliability, and variability perspectives
Technology scaling has resulted in smaller and faster transistors in successive technology
generations. However, transistor power consumption no longer scales commensurately with …
generations. However, transistor power consumption no longer scales commensurately with …
Hayat: Harnessing dark silicon and variability for aging deceleration and balancing
Elevated power densities result in the so-called Dark Silicon constraint that prohibits
simultaneous activation of all the cores in an on-chip system (in the full performance mode) …
simultaneous activation of all the cores in an on-chip system (in the full performance mode) …
Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems
G Liu, J Park, D Marculescu - 2013 IEEE 31st international …, 2013 - ieeexplore.ieee.org
This paper addresses the problem of dynamic thread mapping in heterogeneous many-core
systems via an efficient algorithm that maximizes performance under power constraints …
systems via an efficient algorithm that maximizes performance under power constraints …
Dark silicon as a challenge for hardware/software co-design: Invited special session paper
Dark Silicon refers to the observation that in future technology nodes, it may only be possible
to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache …
to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache …
darknoc: Designing energy-efficient network-on-chip with multi-vt cells for dark silicon
In this paper, we propose a novel NoC architecture, called darkNoC, where multiple layers
of architecturally identical, but physically different routers are integrated, leveraging the extra …
of architecturally identical, but physically different routers are integrated, leveraging the extra …
Variability-aware dark silicon management in on-chip many-core systems
Dark Silicon refers to the constraint that only a fraction of on-chip resources (cores) can be
simultaneously powered-on (running at full performance) in order to stay within the …
simultaneously powered-on (running at full performance) in order to stay within the …
VARSHA: Variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era
N Kapadia, S Pasricha - 2015 Design, Automation & Test in …, 2015 - ieeexplore.ieee.org
With deeper technology scaling accompanied by a worsening power-wall, an increasing
proportion of chip area on a chip multiprocessor (CMP) is expected to be occupied by dark …
proportion of chip area on a chip multiprocessor (CMP) is expected to be occupied by dark …
ASER: Adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era
F Kriebel, S Rehman, D Sun, M Shafique… - Proceedings of the 51st …, 2014 - dl.acm.org
The Dark Silicon provides opportunities to realize Reliability-Heterogeneous Processors
with ISA compatible cores having different levels of protection against reliability threats (like …
with ISA compatible cores having different levels of protection against reliability threats (like …
A multi-version approach to conflict resolution in distributed groupware systems
Groupware systems are a special class of distributed computing systems which support
human-computer-human interaction. Real-time collaborative graphics editors allow a group …
human-computer-human interaction. Real-time collaborative graphics editors allow a group …