gate oxide thin films based on silicon carbide
KO Odesanya, R Ahmad, A Andriyana… - ECS Journal of Solid …, 2022 - iopscience.iop.org
A comprehensive review of the features of silicon carbide (SiC) and various methods of
deposition of gate oxides are presented in this report. The SiC material, which is mostly …
deposition of gate oxides are presented in this report. The SiC material, which is mostly …
[HTML][HTML] Residual strain optimization in 3D MOSFET structures for enhanced mobility via nanoscale heat transfer
JH Hong, MS Kang, I Ha, HL Park, K Park… - Journal of Applied …, 2025 - pubs.aip.org
This study addresses the optimization of strain in continuous MOSFET downscaling,
particularly at the nanoscale, where traditional Fourier models fail due to non-diffusive …
particularly at the nanoscale, where traditional Fourier models fail due to non-diffusive …
Impact of high-k spacer on device performance of nanoscale underlap fully depleted SOI MOSFET
The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to
short channel effects compared to conventional bulk MOSFETs. The inclusion of gate …
short channel effects compared to conventional bulk MOSFETs. The inclusion of gate …
Thin film deposition for front end of line: the effect of the semiconductor scaling, strain engineering and pattern effects
M Belyansky - Handbook of Thin Film Deposition, 2018 - Elsevier
Performance challenges of Moore's Law and continuation of scaling in the microelectronics
industry have a profound effect on chemical vapor deposition (CVD) techniques and …
industry have a profound effect on chemical vapor deposition (CVD) techniques and …
Effects of O2 and N2 Gas Concentration on the Formation of Ho2O3 Gate Oxide on 4H-SiC Substrate
KO Odesanya, R Ahmad, A Andriyana, S Ramesh… - Silicon, 2023 - Springer
In this paper, the impacts of flow concentration of oxynitridation on the structural and
electrical performance of a high-κ Ho2O3 dielectric on n-type 4H-SiC were studied. The …
electrical performance of a high-κ Ho2O3 dielectric on n-type 4H-SiC were studied. The …
Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices
YQ Aguiar, AL Zimpeck, C Meinhardt… - 2017 24th IEEE …, 2017 - ieeexplore.ieee.org
Temperature dependence is of utmost importance for the performance and power
dissipation analysis. This work investigates the temperature dependence of bulk double …
dissipation analysis. This work investigates the temperature dependence of bulk double …
Silicon and germanium vertical super-thin body (VSTB) FET: a comparative performance overview including architectural stress-strain impact
This article aims to develop a comprehensive understanding of the comparative
performance of a vertical super-thin body (VSTB) FET in terms of two device material …
performance of a vertical super-thin body (VSTB) FET in terms of two device material …
Robustness of sub-22nm multigate devices against physical variability
This work provides a detailed set of predictive data about FinFET and Trigate devices
behavior considering process variability effects in ON and OFF currents. These evaluations …
behavior considering process variability effects in ON and OFF currents. These evaluations …
Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET
In this article, surface-potential-based analytical threshold voltage model for underlap Fully
Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two …
Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two …
[PDF][PDF] Low-Power 6T SRAM Cell using 22nm CMOS Technology
N Kumari, V Niranjan - Indian Journal of VLSI Design …, 2022 - ijvlsi.latticescipub.com
Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip
due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell …
due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell …