High-performance and low-power conditional discharge flip-flop
P Zhao, TK Darwish… - IEEE transactions on very …, 2004 - ieeexplore.ieee.org
In this paper, high-performance flip-flops are analyzed and classified into two categories: the
conditional precharge and the conditional capture technologies. This classification is based …
conditional precharge and the conditional capture technologies. This classification is based …
IBM's S/390 G5 microprocessor design
TJ Slegel, RM Averill, MA Check, BC Giamei… - IEEE micro, 1999 - ieeexplore.ieee.org
The IBM S/390 G5 microprocessor in IBM's newest CMOS mainframe system provides more
than twice the performance of the previous generation, the G4. The G5 system offers …
than twice the performance of the previous generation, the G4. The G5 system offers …
[PDF][PDF] Equivalent Elmore delay for RLC trees
YI Ismail, EG Friedman, JL Neves - Proceedings of the 36th annual ACM …, 1999 - dl.acm.org
Closed form solutions for the 50% delay, rise time, overshoots, and settling time of signals in
an RLC tree are presented. These solutions have the same accuracy characteristics as the …
an RLC tree are presented. These solutions have the same accuracy characteristics as the …
A clock distribution network for microprocessors
PJ Restle, TG McNamara, DA Webber… - IEEE Journal of Solid …, 2001 - ieeexplore.ieee.org
A global clock distribution strategy used on several microprocessor chips is described. The
clock network consists of buffered tunable trees or treelike networks, with the final level of …
clock network consists of buffered tunable trees or treelike networks, with the final level of …
A 10-GHz global clock distribution using coupled standing-wave oscillators
A global clock network that incorporates standing waves and coupled oscillators to distribute
a high-frequency clock signal with low skew and low jitter is described. The key design …
a high-frequency clock signal with low skew and low jitter is described. The key design …
Low-power clock branch sharing double-edge triggered flip-flop
In this paper, a new technique for implementing low-energy double-edge triggered flip-flops
is introduced. The new technique employs a clock branch-sharing scheme to reduce the …
is introduced. The new technique employs a clock branch-sharing scheme to reduce the …
Active GHz clock network using distributed PLLs
V Gutnik, AP Chandrakasan - IEEE Journal of Solid-State …, 2000 - ieeexplore.ieee.org
A novel clock network composed of multiple synchronized phase-locked loops is analyzed,
implemented, and tested. Undesirable large-signal stable (mode-locked) states dictate the …
implemented, and tested. Undesirable large-signal stable (mode-locked) states dictate the …
[图书][B] On-chip inductance in high speed integrated circuits
YI Ismail, EG Friedman - 2001 - books.google.com
The appropriate interconnect model has changed several times over the past two decades
due to the application of aggressive technology scaling. New, more accurate interconnect …
due to the application of aggressive technology scaling. New, more accurate interconnect …
[图书][B] Power distribution network design for VLSI
QK Zhu - 2004 - books.google.com
A hands-on troubleshooting guide for VLSI network designers The primary goal in VLSI
(very large scale integration) power network design is to provide enough power lines across …
(very large scale integration) power network design is to provide enough power lines across …
Hogwild++: A new mechanism for decentralized asynchronous stochastic gradient descent
Stochastic Gradient Descent (SGD) is a popular technique for solving large-scale machine
learning problems. In order to parallelize SGD on multi-core machines, asynchronous SGD …
learning problems. In order to parallelize SGD on multi-core machines, asynchronous SGD …