Design of efficient QCA multiplexers

G Cocorullo, P Corsonello, F Frustaci… - International Journal of …, 2016 - Wiley Online Library
A new methodology to realize efficient multiplexers using quantum‐dot cellular automata
(QCA) is presented in this paper. The novel designs here demonstrated fully exploit the …

A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates

A Kumar, RK Nagaria - Analog Integrated Circuits and Signal Processing, 2020 - Springer
In this work, a new technique for domino circuit is proposed to reduce the process variations
and power dissipation with optimized delay for wide fan-in OR logic. Two methods are used …

Low leakage and highly noise immune FinFET-based wide fan-in dynamic logic design

V Mahor, M Pattanaik - Journal of Circuits, Systems and Computers, 2015 - World Scientific
Wide fan-in dynamic logic OR gate has always been an integral part of high speed
microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always …

Reduction of variation and leakage in wide fan-in OR Logic domino gate

A Kumar, RK Nagaria - Integration, 2023 - Elsevier
In this paper, a novel domino gate is proposed to decrease the process variability and
leakage current with enhanced noise margin for wide fan-in OR logic. The process variation …

A 1.2 V-to-0.4 V 3.2 GHz-to-14.3 MHz power-efficient 3-port register file in 65-nm CMOS

K Sarfraz, M Chan - IEEE Transactions on Circuits and Systems …, 2016 - ieeexplore.ieee.org
This paper presents a 44.2-mW 3.2-GHz 3-port register file (RF) that demonstrates
measured operation from 1.2 V down to 0.4 V. The 32-entry× 32-bit/word 2-read/1-write RF …

[PDF][PDF] A Charge-Accumulation Based High-Performance CMOS Circuit

SM Sharroush - Port-Said Engineering Research Journal, 2022 - pserj.journals.ekb.eg
There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide
fan-in suffers from degraded performance. In this paper, a circuit that depends on charge …

A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines

K Sarfraz, M Chan - … 2015-41st European Solid-State Circuits …, 2015 - ieeexplore.ieee.org
This paper presents the highest measured read access frequency for a multi-ported register
file (RF) fabricated in a low-power (LP) 1.2 V TSMC 65nm low-V t CMOS process. Active …

[PDF][PDF] Jordan Journal of Electrical Engineering

SM Sharroush, SF Nafea - Jordan Journal of Electrical Engineering …, 2023 - academia.edu
Domino logic finds a wide variety of applications in both static and dynamic random-access
memories and in high-speed microprocessors. However, the main limitation of the domino …

[PDF][PDF] Golden Research Thoughts

TN Shinde, MLA Yakkaldevi, R Dalvi… - International …, 2014 - papers.ssrn.com
For the first time in the last five decades, quality has become the key slogan in Indian
organizations as they strive for a competitive advantage in an atmosphere characterized by …

[PDF][PDF] An Integrated Switching Technique for Minimizing Power Consumption Using MDFSD in Domino Logic System

J Muralidharan, P Manimegalai - International Journal of Applied …, 2016 - academia.edu
A domino logic technique is designed to meet the critical concern of the VLSI era with
convenience and high microelectronic devices, power consumption of the digital circuit. The …