Multiplication is one of the essential functions in all digital systems. The evaluation of digital
system, have brought out new challenges in VLSI (Very Large Scale Integration) designing …

A technique for efficiently multiplying two signed numbers using limited area and high speed
is presented in this paper. This work uses both the Booth and Vedic multiplication sutra …

This paper presents a modified binary multiplier using Vedic mathematics. The paper
proposes a modification in the previously published Vedic multiplier circuit. The suggested …

Vedic algorithm is beneficial for the application in the design of high‐speed computing and
hardware. This study presents a fast signed binary multiplication structure based on Vedic …

Hardware such as multipliers and dividers is necessary for all electronic systems. This paper
explores Vedic mathematics techniques for high-speed and low-area multiplication. In the …

Immense growth in technology and ever-increasing computational complexities in image
and signal processing algorithms requires robust and efficient hardware software co-design …

The principle of redundant binary representation is used to design power and area efficient
signed Vedic 8× 8 multiplier architecture. The Urdhva Tiryakbhyam Sutra, which extends …

This paper proposes a novel method using Vedic mathematics for calculating the square of
binary numbers. An improved Vedic multiplier architecture is used in the binary squaring …

Nowadays, the requirement for very high-speed operations in processors constantly
increases. Multiplication is a crucial operation in high power-consuming processes such as …

A novel method for squaring binary numbers using Vedic mathematics is proposed in this
paper. The implementation of the binary squaring circuit uses the improved Vedic multiplier …