First worldwide family litigation filed litigation Critical https://patents. darts-ip. com/? family=
52813789&utm_source= google_patent&utm_medium= platform_link&utm_campaign …

2005-08-05 Assigned to PACT XPP TECHNOLOGIES AG reassignment PACT XPP
TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

An internal bus system for DFPs and units with two-or multi-dimensional programmable cell
architectures, for managing large Volumes of data with a high interconnection complexity …

An arrangement and a method are provided for replacing defective units, which can be any
desired unit of a chip (eg, arithmetic and logic units), with a function unit. The arrangement …

An enhanced switch/network adapter port incorporating shared memory resources
(“SNAPM™”) selectively accessible by a direct execution logic element and one or more …

(54) SYSTEM AND METHOD FOR CONVERTING 5,978,588 A* 11/1999
Wallace...................... 717/159 CONTROL FLOW GRAPH 6,023,755 A 2/2000 Casselman …

(57) ABSTRACT A cascadable arithmetic and logic unit (ALU) which is con figurable in
function and interconnection. No decoding of commands is needed during execution of the …

5,831,864 A* 11/1998 Raghunathan et al.......... T16. 2 an internal representation of the
control-dataflow graph that includes one or more dataflow code blocks, and simulating the …

A system and method for compiling computer code written to conform to a high-level
language standard to generate a unified executable containing the hardware logic for a …

Apparatus and methods are disclosed for implementing block-based processors having
custom function blocks, including field-programmable gate array (FPGA) implementations. In …