A system and method for clock phase alignment at a plurality of line cards over a backplane
of a communication system. Phase adjustments are continually made for the clock signals at …

A sampling clock generator generates a sampling clock based on a reference clock and an
internal clock. An internal clock generator causes, during a period in which the sampling …

Various aspects facilitate error reduction for an analog to digital converter (eg, due to
metastability). A digital to analog converter generates a scaled reference voltage based on a …

An apparatus includes a phase locked loop circuit having a phase comparator for
generating a signal indicative of a phase difference between a signal presented to a first …

The present application is a national phase entry under 35 USC S371 of International
Application No. PCT/US2012/028955, filed Mar. 13, 2012, entitled “TEMPERATURE …

A conversion time and an acquisition time of an ADC can be estimated so that a speed of the
ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and …

(21) Appl. No.: 15/169,997(57) ABSTRACT (22) Filed: Jun. 1, 2016 An integrated circuit
apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator …

An integrated circuit comprising, a Voltage regulator circuit and a programmable low power
high-speed current steering logic (LPHCSL) driver circuit coupled to a common supply …

A frequency synthesizer comprising a first phase locked loop (PLL) circuit coupled to receive
a reference frequency signal from a reference oscillator, the first PLL circuit comprising a first …

Aspects of the disclosure provide an analog-to-digital converter (ADC). The ADC includes a
comparator module and a digital-to-analog converter (DAC). The comparator module is …