AC—Clocked power supply DCVSL—Differential Cascode Voltage Switching Logic: Design guidelines...

Design of dynamic digital circuits with n-channel multiple-input floating-gate transistors

G Hang, X Zhou, X Hu - 2014 IEEE 12th international …, 2014 - ieeexplore.ieee.org
Dynamic circuits using n-channel multiple-input floating-gate MOS (FGMOS) transistors to
realize binary and ternary logic are presented. In binary domino circuits, the n-channel …
被引用次数：3 相关文章 所有 3 个版本

A clocked differential switch logic using floating-gate MOS transistors

G Hang, Y Yang, P Zhao, X Hu… - 2013 IEEE 10th …, 2013 - ieeexplore.ieee.org
A novel differential dynamic CMOS logic using multiple-input floating-gate MOS (FGMOS)
transistors is proposed. In this circuit family, a pair of n-channel multiple-input FGMOS pull …
被引用次数：3 相关文章 所有 2 个版本

Novel differential logic using floating-gate MOS transistors

GQ Hang, YN Mo, XC Zhou… - 2012 IEEE 11th …, 2012 - ieeexplore.ieee.org
A new static CMOS differential logic based on multiple-input floating-gate MOS (FGMOS)
transistor is proposed. In this circuit configuration, a pair of n-channel multiple-input FGMOS …
被引用次数：2 相关文章 所有 2 个版本

An Enhanced Dynamic Switch Logic with Floating-Gate MOS Transistors

G Hang, D Zhang, X Zhou, X You - 2013 Ninth International …, 2013 - ieeexplore.ieee.org
A new enhanced dynamic logic using multiple-input floating-gate MOS (FGMOS) transistors
is presented. The circuit technique is designed using an n-channel multiple-input FGMOS …
被引用次数：1 相关文章 所有 4 个版本

Technology management in the knowledge based economy

J van der Pijl, P Ribbers, M Smits - Proceedings of the 35th Annual …, 2002 - computer.org
MapReduce has been proven to be a highly desirable platform for scalable parallel data
analysis. The task scheduling in MapReduce is very crucial for the job execution and has a …
相关文章 所有 7 个版本