Detecting layout hotspots is one of the key problems in physical verification flow. Although
machine learning solutions show benefits over lithography simulation and pattern matching …

With the advancement of very large scale integrated circuits (VLSI) technology nodes,
lithographic hotspots become a serious problem that affects manufacture yield. Lithography …

In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …

Because of the widening sub-wavelength lithography gap in advanced fabrication
technology, lithography hotspot detection has become an essential task in design for …

Yield learning and optimization are critical for advanced IC design and manufacturing.
Recent advance in machine learning has brought a lot of new opportunities in improving the …

With the continuous shrinking of technology nodes, lithography hotspot detection and
elimination in the physical verification phase is of great value. Recently machine learning …

As the physical design of semiconductors continues to shrink, the lithography process is
becoming more sensitive to layout design. Identifying lithography hotspots (HSs) in the …

Under the low-k1 lithography process, lithography hotspot detection and elimination in the
physical verification phase have become much more important for reducing the process …

In this paper, we survey key design for manufacturing issues for extreme scaling with
emerging nanolithography technologies, including double/multiple patterning lithography …

As the circuit feature size continuously shrinks down, hotspot detection has become a more
challenging problem in modern DFM flows. Developed deep learning techniques have …