Spade: A flexible and scalable accelerator for spmm and sddmm
The widespread use of Sparse Matrix Dense Matrix Multiplication (SpMM) and Sampled
Dense Matrix Dense Matrix Multiplication (SDDMM) kernels makes them candidates for …
Dense Matrix Dense Matrix Multiplication (SDDMM) kernels makes them candidates for …
Menda: A near-memory multi-way merge solution for sparse transposition and dataflows
Near-memory processing has been extensively studied to optimize memory intensive
workloads. However, none of the proposed designs address sparse matrix transposition, an …
workloads. However, none of the proposed designs address sparse matrix transposition, an …
SparseAdapt: Runtime control for sparse linear algebra on a reconfigurable accelerator
Dynamic adaptation is a post-silicon optimization technique that adapts the hardware to
workload phases. However, current adaptive approaches are oblivious to implicit phases …
workload phases. However, current adaptive approaches are oblivious to implicit phases …
Special session: Towards an agile design methodology for efficient, reliable, and secure ML systems
The real-world use cases of Machine Learning (ML) have exploded over the past few years.
However, the current computing infrastructure is insufficient to support all real-world …
However, the current computing infrastructure is insufficient to support all real-world …
Cosparse: A software and hardware reconfigurable spmv framework for graph analytics
Sparse matrix-vector multiplication (SpMV) is a critical building block for iterative graph
analytics algorithms. Typically, such algorithms have a varying active vertex set across …
analytics algorithms. Typically, such algorithms have a varying active vertex set across …
Versa: A 36-core systolic multiprocessor with dynamically reconfigurable interconnect and memory
We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically
reconfigurable interconnects and memory. Versa leverages reconfigurable functional units …
reconfigurable interconnects and memory. Versa leverages reconfigurable functional units …
An adjustable farthest point sampling method for approximately-sorted point cloud data
Sampling is an essential part of raw point cloud data processing, such as in the popular
PointNet++ scheme. Farthest Point Sampling (FPS), which iteratively samples the farthest …
PointNet++ scheme. Farthest Point Sampling (FPS), which iteratively samples the farthest …
Blocks: Challenging simds and vliws with a reconfigurable architecture
M Wijtvliet, A Kumar, H Corporaal - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Demand for coarse grain reconfigurable architectures (CGRAs) has significantly increased
in recent years as architectures need to be both energy efficient and flexible. However, most …
in recent years as architectures need to be both energy efficient and flexible. However, most …
OnSRAM: Efficient inter-node on-chip scratchpad management in deep learning accelerators
Hardware acceleration of Artificial Intelligence (AI) workloads has gained widespread
popularity with its potential to deliver unprecedented performance and efficiency. An …
popularity with its potential to deliver unprecedented performance and efficiency. An …
Rewriting History: Repurposing Domain-Specific CGRAs
Coarse-grained reconfigurable arrays (CGRAs) are domain-specific devices promising both
the flexibility of FPGAs and the performance of ASICs. However, with restricted domains …
the flexibility of FPGAs and the performance of ASICs. However, with restricted domains …