Power grid analysis benchmarks

SR Nassif - 2008 Asia and South Pacific Design Automation …, 2008 - ieeexplore.ieee.org
Benchmarks are an immensely useful tool in performing research since they allow for rapid
and clear comparison between different approaches to solving CAD problems. Recent …

Redundantly tied metal fill for IR-drop and layout density optimization

HKS Leung - US Patent 7,240,314, 2007 - Google Patents
An integrated circuit and a method for using metal fill geometries to reduce the Voltage drop
in power meshes. Metal fill geometries are connected to the power mesh using vias or wires …

Design and Analysis of Power Distribution Networks in VLSI Circuits.

S Pant - 2008 - deepblue.lib.umich.edu
Rapidly switching currents of the on-chip devices can cause fluctuations in the supply
voltage which can be classified as IR and Ldi/dt drops. The voltage fluctuations in a supply …

Redundancy-aware electromigration checking for mesh power grids

S Chatterjee, M Fawaz, FN Najm - 2013 IEEE/ACM …, 2013 - ieeexplore.ieee.org
Electromigration (EM) is re-emerging as a significant problem in modern integrated circuits
(IC). Especially in power grids, due to shrinking wire widths and increasing current densities …

Simulation algorithms with exponential integration for time-domain analysis of large-scale power delivery networks

H Zhuang, W Yu, SH Weng, I Kang… - … on Computer-Aided …, 2016 - ieeexplore.ieee.org
We design an algorithmic framework using matrix exponentials for time-domain simulation of
power delivery network (PDN). Our framework can reuse factorized matrices to simulate the …

Fast vectorless power grid verification using an approximate inverse technique

NH Abdul Ghani, FN Najm - Proceedings of the 46th Annual Design …, 2009 - dl.acm.org
Power grid verification in modern integrated circuits is an integral part of early system design
where adjustments can be most easily incorporated. In this work, we describe an early …

Early-stage power grid analysis for uncertain working modes

H Qian, SR Nassif, SS Sapatnekar - Proceedings of the 2004 …, 2004 - dl.acm.org
High performance integrated circuits are now reaching the 100-plus watt regime, and power
delivery and power grid signal integrity have become critical. Analyzing the performance of …

Verification and codesign of the package and die power delivery system using wavelets

IA Ferzli, E Chiprout, FN Najm - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
As part of the design of large integrated circuits, one must verify that the power delivery
network provides supply and ground voltages to the circuit that are within specified ranges …

Static timing analysis considering power supply variations

S Pant, D Blaauw - ICCAD-2005. IEEE/ACM International …, 2005 - ieeexplore.ieee.org
Power supply integrity verification has become a key concern in high performance designs.
In deep submicron technologies, power supply noise can significantly increase the circuit …

A spectral graph sparsification approach to scalable vectorless power grid integrity verification

Z Zhao, Z Feng - Proceedings of the 54th Annual Design Automation …, 2017 - dl.acm.org
Vectorless integrity verification is becoming increasingly critical to robust design of
nanoscale power delivery networks (PDNs). To dramatically improve efficiency and …