High density interconnect system for IC packages and interconnect assemblies

WR Bottoms, FC Chong, S Mok, D Modlin - US Patent 7,579,848, 2009 - Google Patents
An improved interconnection system is described, such as for electrical contactors and
connectors, electronic device or module package assemblies, socket assemblies, and/or …

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

MS Bakir, HA Reed, HD Thacker… - … on Electron Devices, 2003 - ieeexplore.ieee.org
Sea of Leads (SoL) is an ultrahigh density (> 10/sup 4//cm/sup 2/) compliant chip
input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend …

Design, fabrication, and characterization of dense compressible microinterconnects

PK Jo, M Zia, JL Gonzalez, H Oh… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
This paper presents gold passivated NiW compressible microinterconnects (CMIs) with 75
μm height and 150 μm in-line pitch. The CMIs are batch fabricated using CMOS-compatible …

/spl beta/-Helix: a lithography-based compliant off-chip interconnect

Q Zhu, L Ma, SK Sitaraman - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
Microsystems packages continue to demand lower cost, higher reliability, better
performance and smaller size. Compliant wafer-level interconnects show great potential for …

Highly elastic gold passivated mechanically flexible interconnects

C Zhang, HS Yang, MS Bakir - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A wafer-level batch fabricated mechanically flexible interconnect (MFI) technology with 65-
μm vertical elastic range of motion is experimentally demonstrated. A metal alloy (NiW) with …

Response surface and multiobjective optimization methodology for the design of compliant interconnects

W Chen, SK Sitaraman - IEEE Transactions on Components …, 2014 - ieeexplore.ieee.org
Compliant off-chip interconnects have both in-plane and out-of-plane compliance and are
able to accommodate the differential deflection between the die and the substrate or …

Thermomechanical analysis and package-level optimization of mechanically flexible interconnects for interposer-on-motherboard assembly

MO Hossen, JL Gonzalez… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper explores different means by which the interconnect reliability is improved and
interposer warpage is decreased for an interposer-to-board integration platform using …

Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics

MS Bakir, B Dang, R Emery… - IEEE transactions on …, 2005 - ieeexplore.ieee.org
Sea of leads (SoL) process integration for the series of steps required to transform a fully
intact die at the wafer level to a die that is assembled onto a board is described. The primary …

Package with integrated wick layer and method for heat removal

C Hu, RD Emery - US Patent 7,095,111, 2006 - Google Patents
A package for a die includes a porous wick layer disposed between the die and a substrate.
A sealed chamber between the die and substrate includes a phase-change fluid to transfer …

Massively parallel interface for electronic circuit

FC Chong, S Mok - US Patent 7,403,029, 2008 - Google Patents
Several embodiments of massively parallel interface structures are disclosed, which may be
used in a wide variety of permanent or temporary applications, such as for interconnecting …