[图书][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
Overcoming variations in nanometer-scale technologies
SS Sapatnekar - IEEE Journal on Emerging and Selected …, 2011 - ieeexplore.ieee.org
Nanometer-scale circuits are fundamentally different from those built in their predecessor
technologies in that they are subject to a wide range of new effects that induce on-chip …
technologies in that they are subject to a wide range of new effects that induce on-chip …
[图书][B] Graphs in VLSI
R Bairamkulov, EG Friedman - 2023 - Springer
Advances in semiconductor fabrication technology have produced explosive growth in the
number of transistors within an integrated circuit (IC). Modern devices consist of dozens of …
number of transistors within an integrated circuit (IC). Modern devices consist of dozens of …
Partition-based algorithm for power grid design using locality
J Singh, SS Sapatnekar - IEEE Transactions on Computer …, 2006 - ieeexplore.ieee.org
This paper presents an efficient heuristic algorithm, which employs successive partitioning
and grid-refinement scheme, for designing the power distribution network of a chip. In an …
and grid-refinement scheme, for designing the power distribution network of a chip. In an …
Fast placement optimization of power supply pads
Y Zhong, MDF Wong - 2007 Asia and South Pacific Design …, 2007 - ieeexplore.ieee.org
Power grid networks in VLSI circuits are required to provide adequate input supply to ensure
reliable performance. In this paper, we propose algorithms to find the placement of power …
reliable performance. In this paper, we propose algorithms to find the placement of power …
Power Aware Placement of On-Chip Voltage Regulators
R Bairamkulov, EG Friedman - IEEE Transactions on Computer …, 2023 - ieeexplore.ieee.org
In traditional power delivery networks, the on-chip supply voltage is provided by board-level
converters. Due to the significant distance between the converter and the load, variations in …
converters. Due to the significant distance between the converter and the load, variations in …
Supply voltage degradation aware analytical placement
Increasingly significant power/ground supply voltage degradation in nanometer VLSI
designs leads to system performance degradation and even malfunction. Existing …
designs leads to system performance degradation and even malfunction. Existing …
Walking pads: Fast power-supply pad-placement optimization
We propose a novel C4 pad placement optimization framework for 2D power delivery grids:
Walking Pads (WP). WP optimizes pad locations by moving pads according to the “virtual …
Walking Pads (WP). WP optimizes pad locations by moving pads according to the “virtual …
Power network analyzer for an integrated circuit design
PHY Tai, YM Jiang, SH Kwon - US Patent 7,797,654, 2010 - Google Patents
A 5,598,348 A 1/1997 Rusu et al. 5,808,900 A 9, 1998 Buer et al. 5,933,358 A 8, 1999 Koh
et al. 6,043,672 A 3/2000 Sugasawara 6,202,191 B1 3/2001 Filippi et al. 6,202,196 B1 …
et al. 6,043,672 A 3/2000 Sugasawara 6,202,191 B1 3/2001 Filippi et al. 6,202,196 B1 …
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion
An efficient pad assignment algorithm to minimize voltage drop on a power distribution
network is proposed. Combination of the successive pad assignment (SPA) and the …
network is proposed. Combination of the successive pad assignment (SPA) and the …