A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications

L Liu, J Zhu, Z Li, Y Lu, Y Deng, J Han, S Yin… - ACM Computing …, 2019 - dl.acm.org
As general-purpose processors have hit the power wall and chip fabrication cost escalates
alarmingly, coarse-grained reconfigurable architectures (CGRAs) are attracting increasing …

An overview of low-power techniques for field-programmable gate arrays

J Lamoureux, W Luk - 2008 NASA/ESA Conference on …, 2008 - ieeexplore.ieee.org
This paper provides an overview of low-power techniques for field-programmable gate
arrays (FPGAs). It covers system-level design techniques and device-level design …

[图书][B] Top-down digital VLSI design: from architectures to gate-level circuits and FPGAs

H Kaeslin - 2014 - books.google.com
Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a
unique approach to learning digital design. Developed from more than 20 years teaching …

Evaluating programmable architectures for imaging and vision applications

A Vasilyev, N Bhagdikar, A Pedram… - 2016 49th Annual …, 2016 - ieeexplore.ieee.org
Algorithms for computational imaging and computer vision are rapidly evolving, and
hardware must follow suit: the next generation of image signal processors (ISPs) must be …

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane

J Deng, X Tang, J Zhang, Y Li, L Zhang, B Han… - Proceedings of the 56th …, 2023 - dl.acm.org
Spatial architecture is a high-performance architecture that uses control flow graphs and
data flow graphs as the computational model and producer/consumer models as the …

An ILP formulation for task mapping and scheduling on multi-core architectures

Y Yi, W Han, X Zhao, AT Erdogan… - … Design, Automation & …, 2009 - ieeexplore.ieee.org
Multi-core architectures are increasingly being adopted in the design of emerging complex
embedded systems. Key issues of designing such systems are on-chip interconnects …

A heterogeneous reconfigurable cell array for MIMO signal processing

C Zhang, L Liu, D Marković… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper presents a heterogeneous reconfigurable cell array, designed for high-
throughput baseband processing of multiple-input multiple-output (MIMO) systems. To …

[PDF][PDF] Reduction of power consumption in FPGAs-an overview

N Grover, MK Soni - International journal of information engineering …, 2012 - mecs-press.org
Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital
systems due to their flexibility, programmability and low end product life cycle. In more than …

Towards designing asynchronous microprocessors: From specification to tape-out

Z Tabassam, SR Naqvi, T Akram, M Alhussein… - IEEE …, 2019 - ieeexplore.ieee.org
Proceeding miniaturization in the VLSI circuits continues to pose challenges to the
conventionally used synchronous design style in microprocessors. These include the …

Multi-core architectures with dynamically reconfigurable array processors for the WIMAX physical layer

W Han, Y Yi, M Muir, I Nousias, T Arslan… - 2008 Symposium on …, 2008 - ieeexplore.ieee.org
Wireless internet access technologies have significant market potential, especially the
WiMAX protocol which can offer data rate of tens of Mbps. A significant demand for …