With the advent of small, battery-powered devices, power efficiency has become of
paramount importance. For analog-to-digital converters (ADCs), the successive …

This work presents a 14-bit oversampled successive-approximation-register (SAR) analog-
to-digital converter (ADC) with mismatch error shaping (MES) and pre-comparison …

Despite recent developments in automated analog sizing and analog layout generation,
there is doubt whether analog design automation techniques could scale to system-level …

The input capacitance of the SAR ADC is considered a drawback in many applications. In
this paper, a 12-bit low-power SAR ADC with low-input capacitance is proposed. The ADC is …

This brief presents a 10.5-bit 10 MS/s successive-approximation-register (SAR) analog-to-
digital converter (ADC) with input range (IR). By pre-setting and resetting the most significant …

This paper proposes a differential 10-bit 1 MS/s successive approximation register (SAR)
analog to digital converter (ADC) with input range (IR) extension. Employing 512 capacitor …

This paper presents a 13-tap FIR filter and an IIR filter embedded in a 10-bit SAR ADC for
wireless communications chip. The IIR filter can be inherently realized through reusing the …

This brief presents four small-area SAR ADCs with a resolution from 8 to 11 bits. Two area-
saving techniques are utilized. First, the DAC layout is implemented with custom designed …

A 12-bit low-power SAR ADC with low-input capacitance is proposed. The topology exploits
a structure with separate sample & hold and DAC blocks, separated block SAR, to achieve …

This work presents a reconfigurable delay and redundancy technique, which relaxes the
reference driver requirements for a charge-redistribution SAR ADC. By selectively adding …