A 12-GS/s 12-b 4 Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer
This article presents a 12-GS/s 12-bit time-interleaved (TI) pipelined analog-to-digital
converter (ADC), which utilizes a global dither injection (GDI) scheme to facilitate an input …
converter (ADC), which utilizes a global dither injection (GDI) scheme to facilitate an input …
A 10-mW 10-ENoB 1-GS/s ring-amp-based pipelined TI-SAR ADC with split MDAC and switched reference decoupling capacitor
This article presents a 12-bit 1-GS/s ring-amp-based analog-to-digital converter (ADC) with
a pipelined and time-interleaved successive approximation register (TI-SAR) hybrid …
a pipelined and time-interleaved successive approximation register (TI-SAR) hybrid …
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, ringamp-based pipelined-SAR ADC With background calibration and dynamic reference regulation in 16-nm CMOS
This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed
architectural tradeoffs thanks to the use of ring amplification and background calibration. It …
architectural tradeoffs thanks to the use of ring amplification and background calibration. It …
A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer
Ring amplifier (RingAmp)-based multiplying digital-to-analog converters (MDACs) feature
high energy efficiency and linearity; however, their process, supply voltage, and temperature …
high energy efficiency and linearity; however, their process, supply voltage, and temperature …
A single-channel voltage-scalable 8-GS/s 8-b> 37.5-dB SNDR time-domain ADC with asynchronous pipeline successive approximation in 28-nm CMOS
This article presents a single-channel voltage-scalable 8-GS/s 8-b time-domain analog-to-
digital-converter (TD-ADC). It breaks the speed limit of traditional TD-ADC by leveraging …
digital-converter (TD-ADC). It breaks the speed limit of traditional TD-ADC by leveraging …
Analog Triggered Asynchronous Clocking Technique Based on the Ring Amplifier in Pipeline ADC
Z Tang, G Chen, Q Liu, J Zhang… - 2022 IEEE 8th …, 2022 - ieeexplore.ieee.org
A design technique for the analog triggered asynchronous clocking control technique for the
pipeline ADC is presented, which is convenient for the realization of highly integrated ADCs …
pipeline ADC is presented, which is convenient for the realization of highly integrated ADCs …