Method and apparatus for specifying encoded sub-networks
S Teig, A Hetzel - US Patent 7,076,760, 2006 - Google Patents
A method is provided for pre-tabulating sub-networks that (1) generates a sub-network that
performs a function,(2) generates a parameter based on this function, and (3) stores the sub …
performs a function,(2) generates a parameter based on this function, and (3) stores the sub …
Method and apparatus for routing a set of nets
S Teig, A Caldwell - US Patent 6,877,146, 2005 - Google Patents
703/13–17; 712/207 (57) ABSTRACT (56) References Cited One embodiment of the
invention is a method of Specifying routes for a group of nets. The method Specifies a total …
invention is a method of Specifying routes for a group of nets. The method Specifies a total …
Method and apparatus for evaluating logic states of design nodes for cycle-based simulation
LT Chen, TM McWilliams - US Patent 7,076,416, 2006 - Google Patents
Modern high performance microprocessors have an ever increasing number of circuit
elements and an ever-rising clock frequency. Also, as the number of circuits that can be …
elements and an ever-rising clock frequency. Also, as the number of circuits that can be …
Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
BW McGaughy, P Karhade, P Wan, M Singh - US Patent 7,143,021, 2006 - Google Patents
A machine-implemented, simulations-supporting system creates a hierarchy of data
structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso …
structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso …
Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph
Configuration data for an integrated circuit may be generated using logic design equipment
to implement an circuit design on the integrated circuit. Implementing the circuit design may …
to implement an circuit design on the integrated circuit. Implementing the circuit design may …
Method and system for fault-tolerant static timing analysis
DJ Hathaway, PJ Osler - US Patent 6,795,951, 2004 - Google Patents
(57) ABSTRACT 4.263, 651. A 4/1981 Donath et al. 4.924, 430 A 5/1990 Zasio et al. A
method and System for performing fault tolerant Static 5,365,463 A 11/1994 Donath et al …
method and System for performing fault tolerant Static 5,365,463 A 11/1994 Donath et al …
Reduced pessimism clock gating tests for a timing analysis tool
DJ Hathaway, JP Soreff, NR Vanderschaaf… - US Patent …, 2004 - Google Patents
2. Description of the Related Art Integrated circuit (IC) manufacturers have continuously
Sought to build Smaller and more efficient integrated circuit chips that contain an increasing …
Sought to build Smaller and more efficient integrated circuit chips that contain an increasing …
Method and apparatus for pre-tabulating sub-networks
S Teig, A Hetzel - US Patent 8,151,227, 2012 - Google Patents
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This
method (1) generates a sub-network that performs a function,(2) generates a parameter …
method (1) generates a sub-network that performs a function,(2) generates a parameter …
Method and apparatus for performing technology mapping
S Teig, A Hetzel - US Patent 6,990,650, 2006 - Google Patents
US6990650B2 - Method and apparatus for performing technology mapping - Google Patents
US6990650B2 - Method and apparatus for performing technology mapping - Google Patents …
US6990650B2 - Method and apparatus for performing technology mapping - Google Patents …
Method and apparatus for pre-tabulating sub-networks
S Teig, A Hetzel - US Patent 7,398,503, 2008 - Google Patents
A method for pre-tabulating sub-networks that (1) generates a sub-network that performs a
function,(2) generates a parameter based on this function, and (3) stores the sub-network …
function,(2) generates a parameter based on this function, and (3) stores the sub-network …