(51) Int. Cl. A charge trapping floating gate is described with asymmetric GIC I6/06(2006.01)
tunneling barriers. The memory cell includes a source region HOIL 29/788(2006.01) and a …

Memory cells comprising: a semiconductor substrate having a source region and a drain
region disposed below a surface of the substrate and separated by a channel region; a …

(57) ABSTRACT A vertical channel memory including a substrate, a channel, a multi-layer
structure, a gate, a first terminal and a second terminal is provided. The channel protrudes …

3/2007 Shih et al. 4,630,086 A 12/1986 Sato et al. 2007, 0120179 A1 5, 2007 Park et al.
5,286,994 A 2f1994 Ozawa et al. 2007, 0138539 A1 6, 2007 Wu et al. 5,319,229 A 6/1994 …

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5,515,324 A 5, 1996 Tanaka et al. 6,897,533 B1 5/2005 Yang et al. 5,602,775 A 2, 1997 Vo …

Jan. 3, 2006, now Pat. No. 7,315,474, application No.(74) Attorney, Agent, or Firm—
McClure, Qualey & 12/056,489, which is a continuation-in-part of Rodack, LLP application …

A memory device includes an array of strings of memory cells. The device includes a
plurality of stacks of conductive strips separated by insulating material, including at least a …

This paper reports a new nanocrystal quantum-dot (NC-QD)-based tunable on-chip
electrostatic discharge (ESD) protection mechanism and structures. Experiments validated …

5,981,404 A 1 1/1999 Sheng et al. ductor Surface overlying the dielectric charge trapping
struc ture and the channel Surface of the channel region, and the ratio of the area A2 to the …

With advanced lithographic nodes featuring a half-pitch of 30 nm or less, charge trapping
NAND memory has neighboring cells sufficiently close together that fringing fields from a …