Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book
on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest …

VLSI design is probably the most fascinating application area of combinatorial optimization.
Virtually all classical combinatorial optimization problems, and many new ones, occur …

Circuit optimization is essential to minimize power consumption of designs while satisfying
timing constraints. The CAD problem focused on in the ISPD-2012 Contest is simultaneous …

The well-studied gate-sizing optimization is a major contributor to IC power-performance
tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of …

Most circuit sizing tools calculate the tradeoff between each gate's delay and power or area,
and then greedily change the gate with the best tradeoff. We show this is suboptimal. Instead …

This paper presents a fast and effective approach to gate-version selection and threshold
voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load …

Optimizing timing is critical to the design closure of integrated circuits (ICs). However, most
existing algorithms for circuit placement focus on the optimization of wirelength instead of …

Gate Sizing is an important step in logic synthesis, where the cells are resized to optimize
metrics such as area, timing, power, leakage, etc. In this work, we consider the gate sizing …

Gate sizing and threshold voltage selection is an important step in the VLSI design process
to optimize power and performance of a given netlist. In this paper, we provide an overview …

It is becoming more and more important to design high performance designs with as low
power as possible. In this paper, we study the gate sizing and device technology selection …