This book discusses new techniques for detecting, controlling, and exploiting the impacts of
temperature variations on nanoscale circuits and systems. A new sensor system is …

Dynamic thermal management techniques require accurate runtime temperature information
in order to operate effectively and efficiently. In this paper, we propose two novel solutions …

3D integration of multiple active layers into a single chip is a viable technique that greatly
reduces the length of global wires by providing vertical connections between layers …

In this paper, we study the buffered clock tree synthesis problem under thermal variations for
3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides a …

On-chip temperature gradient emerged as a major design concern for high performance
integrated circuits for the current and future technology nodes. Clock skew is an undesirable …

A robust physical design of 3-D IC requires investigation on through-silicon via (TSV). The
large temperatures and stress gradients can severely affect TSV delay with large variation …

As combinations of signoff corners grow in modern SoCs, minimization of clock skew
variation across corners is important. Large skew variation can cause difficulties in multi …

High-performance clock distribution has been a challenge for nearly three decades. During
this time, clock synthesis tools and algorithms have strove to address a myriad of important …

This paper addresses a fundamental problem of zero skew clock tree embedding problem in
3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree …

The thermal gradients existing in high-performance circuits may significantly affect their
timing behavior, in particular, by increasing the skew of the clock net and/or altering …