The many-core revolution brought forward by recent advances in computer architecture has
created immense challenges in the writing of parallel programs for High Performance …

The recent evolution of many-core architectures has resulted in chips where the number of
processor elements (PEs) are in the hundreds and continue to increase every day. In …

Algorithm implementation efficiency is key to delivering high-performance computing
capabilities to demanding, high throughput DoD signal and image processing applications …

This paper provides a discussion on the shortcomings of traditional static optimization
techniques when used in the context of many-core architectures. We argue that these …

Summary form only given. The popularity of serial execution paradigms in the High
Performance Computing (HPC) field greatly hinders the ability of computational scientists to …

This paper provides an extended description of the design and implementation of the Time
Iterated Dependency Flow (TIDeFlow) execution model. TIDeFlow is a dataflow-inspired …

We propose a relaxed concurrent queue for Graphic Processing Units (GPUs) which
supports groups of unordered enqueue and/or dequeue operations. When the group size is …

In this paper, we propose a new register file architecture called the register file extension for
multi-word and long-word operation (RFEMLO) to accelerate both symmetric and …

TIDeFlow: A dataflow-inspired execution model for High Performance Computing programs
Page 1 TIDEFLOW: A DATAFLOW-INSPIRED EXECUTION MODEL FOR HIGH …

The recent evolution of many-core architectures has resulted in chips where the number of
processor elements (PEs) are in the hundreds and continue to increase every day. In …