Processor core clock rate selection

A Wolfe, T Conte - US Patent 9,519,305, 2016 - Google Patents
Techniques described herein generally relate to multi-core processors including two or more
processor cores. Example embodiments may set forth devices, methods, and computer …

System and method for selecting a power management configuration in a multi-core environment according to various operating conditions such as voltage, frequency …

Y Bai, M Moncrieffe, B Morgan, SB Peirce… - US Patent …, 2014 - Google Patents
BACKGROUND Unless otherwise indicated herein, the approaches described in this section
are not prior art to the claims in the present disclosure and are not admitted to be prior art by …

Processor control system

V Hanumaiah, S Vrudhula, B Gaudette - US Patent 10,133,323, 2018 - Google Patents
A control system for use with a processor includes:(i) a controller configured to receive
prediction information for a predicted temperature associated with the processor, and to …

Determining parameters that affect processor energy efficiency

V Hanumaiah, S Vrudhula - US Patent 9,933,825, 2018 - Google Patents
An example process for controlling a processor may include:(i) obtaining parameters
associated with operation of a processor, where each of the parameters has a different time …

Processor power and performance manager

J Jane, G Avkarogullari, E Sunalp - US Patent 9,329,663, 2016 - Google Patents
BACKGROUND This disclosure relates generally to the management of power consumption
and performance of integrated circuits and systems employing such integrated circuits. As …

Processor core clock rate selection

A Wolfe, T Conte - US Patent 8,751,854, 2014 - Google Patents
Techniques described herein generally relate to multi-core processors including two or more
processor cores. Example embodiments may set forth devices, methods, and computer …

Systems and methods for power optimization using throughput feedback

VR Venumuddala, N Duvvuru, GP Srivastava - US Patent 9,436,263, 2016 - Google Patents
BACKGROUND One common technique for optimizing power consump tion for a processor
is dynamic voltage and frequency scaling (DVFS). In DVFS, the voltage and operating fre …

Managing performance policies based on workload scalability

PS Diefenbaugh, AD Henroid, E Weissmann… - US Patent …, 2015 - Google Patents
2. Discussion Computing platforms may manage processor performance by entering various
performance states that range from rela tively high operating frequency and power …

System and method for selecting a power management configuration in a multi-core environment to balance current load demand and required power consumption

Y Bai, M Moncrieffe, B Morgan, SB Peirce… - US Patent …, 2015 - Google Patents
BACKGROUND Unless otherwise indicated herein, the approaches described in this section
are not prior art to the claims in the present disclosure and are not admitted to be prior art by …

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

A Mathuriya, CB Wilkerson, RK Dokania… - US Patent …, 2024 - Google Patents
A packaging technology to improve performance of an AI processing system resulting in an
ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first …