Routing algorithms play a crucial role in the performance of Network-on-Chip (NoC)-based
Multi-Processor Systems-on-Chip (MPSoC). However, the selection of appropriate and …

A path profile determines how many times each acyclic path in a routine executes. This type
of profiling subsumes the more common basic block and edge profiling, which only …

Abstract Networks− on− chip (NoC) are an alternative to alleviate the problems of legacy
interconnect fabrics. However, many emerging technology NoC are developed and are now …

Increasing fault rates in current and future technology nodes coupled with on-chip
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …

Increasing communication overheads are already threatening computer system scaling. One
approach to dramatically reduce communication overheads is waferscale processing …

Future SoCs are expected to have irregular onchip topologies, either at design time due to
heterogeneity in the size of core/accelerator tiles, or at runtime due to link/node failures or …

This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in
network-on-chips. The algorithm is the first to provide all of the following properties at the …

The messages exchanged in computational systems fall into two broad categories: data and
control messages. Data messages transport data exchanged between tasks at the …

Demand for server memory capacity and performance is rapidly increasing due to
expanding working set sizes of modern applications, such as big data analytics, inmemory …

The expected low reliability of the silicon substrate at upcoming technology nodes presents
a key challenge for digital system designers. Networks-on-chip (NoCs) are especially …