Noise analysis of regenerative comparators for reconfigurable ADC architectures
P Nuzzo, F De Bernardinis, P Terreni… - … on Circuits and …, 2008 - ieeexplore.ieee.org
The need for highly integrable and programmable analog-to-digital converters (ADCs) is
pushing towards the use of dynamic regenerative comparators to maximize speed, power …
pushing towards the use of dynamic regenerative comparators to maximize speed, power …
A novel convolution computing paradigm based on NOR flash array with high computing speed and energy efficiency
Convolution is one of the key operations in signal processing and machine learning
applications. In this paper, we propose a novel convolution computing paradigm based on …
applications. In this paper, we propose a novel convolution computing paradigm based on …
A 150 MS/s 133W 7 bit ADC in 90 nm Digital CMOS
G Van der Plas, B Verbruggen - IEEE Journal of Solid-State …, 2008 - ieeexplore.ieee.org
In recent years the energy efficiency of A/D converters has been improved significantly. Only
5 years ago [3] an energy efficiency of 1 pJ/conversion step was considered state-of-the-art …
5 years ago [3] an energy efficiency of 1 pJ/conversion step was considered state-of-the-art …
A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS
P Nuzzo, C Nani, C Armiento… - … on Circuits and …, 2011 - ieeexplore.ieee.org
A successive approximation analog-to-digital converter (ADC) architecture is presented that
programs its comparator threshold at runtime to approximate the input signal via binary …
programs its comparator threshold at runtime to approximate the input signal via binary …
A 2.2 mW 1.75 GS/s 5 bit folding flash ADC in 90 nm digital CMOS
A 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding technique is presented. The 2X
folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces …
folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces …
A reconfigurable, 130 nm CMOS 108 pJ/pulse, fully integrated IR-UWB receiver for communication and precise ranging
N Van Helleputte, M Verhelst… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
This paper presents a fully integrated flexible ultra-low power UWB impulse radio receiver,
capable of cm-accurate ranging. Ultra-low-power consumption is achieved by employing the …
capable of cm-accurate ranging. Ultra-low-power consumption is achieved by employing the …
A 700 μW 1GS/s 4-bit folding-flash ADC in 65nm CMOS for wideband wireless communications
We present the design of a low-power 4-bit 1GS/s folding-flash ADC with a folding factor of
two in standard 65nm CMOS technology. The design of a new unbalanced double-tail …
two in standard 65nm CMOS technology. The design of a new unbalanced double-tail …
A single-bit 500 KHz-10 MHz multimode power-performance scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm digital CMOS
P Crombez, G Van der Plas… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
Wireless environments, high data rates and increased digitization require A/D converters
with high dynamic range and large bandwidth at the lowest possible power consumption. A …
with high dynamic range and large bandwidth at the lowest possible power consumption. A …
A CMOS ultra-wideband receiver for low data-rate communication
A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate
applications. A topology selection study demonstrates that the quadrature analog correlation …
applications. A topology selection study demonstrates that the quadrature analog correlation …
A 4-bit, 1.6 GS/s low power flash ADC, based on offset calibration and segmentation
M Chahardori, M Sharifkhani… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which
masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced …
masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced …