Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …

L2 cache memories are being adopted in the embedded systems for high performance,
which, however, increases energy consumption due to their large sizes. We propose a low …

A leakage current compensation design for nanoscale SRAMs is proposed in this paper.
The proposed compensation design is composed of a leakage current sensor, which …

An integrated static random access memory (SRAM) compiler is proposed to reduce both
leakage and dynamic power at circuit and architectural level. Based on source biasing …

For low voltage CMOS static random access memory (SRAM) cells, the leakage current on
bit-lines will slow down the reading operation and even lead to error reading. Herein we …

In this paper, the timing performance and power dissipation of 6T static random-access
memory (SRAM) cell for different technology nodes are observed, and the impact of varying …

In this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to
improve the write features of the SRAM cell, a negative voltage is applied to one of the …

While MOSFET miniaturization continues to face increased challenges related to process
variations, supply voltage scaling and leakage currents, exploratory devices such as …

Corner-case analysis is a well-known technique to cope with occasional deviations
occurring during the manufacturing process of semiconductors. However, the increasing …

Information and communication technology (ICT) can cause rapid development in
government processes, especially in developing countries like Nepal. ICT strategies and ICT …