Timed automata are a common formalism for the verification of concurrent systems subject to
timing constraints. They extend finite-state automata with clocks, that constrain the system …

Product detection based on state abstraction technologies in the software product line (SPL)
is more complex when compared to a single system. This variability constitutes a new …

In this paper we define Satisfiability Modulo Theory based (SMT-based) and SAT-based
bounded model checking (BMC) methods for the existential fragment of Weighted Epistemic …

The paper deals with symbolic approach to bounded model checking (BMC) for metric
temporal logic with epistemic operators (MTLK) that is interpreted over timed interpreted …

This article introduces a new method for modelling and verifying the execution of timed
security protocols (TSPs) and their time-dependent security properties. The method, which is …

In this paper, we present the SMT-based bounded model checking (BMC) method for Timed
Real-Weighted Interpreted Systems and for the existential fragment of the Weighted …

We present a satisfiability modulo theories based bounded model checking (SMT-based
BMC) method for timed interpreted systems (TIS) and for properties expressible in the …

The use of automated verification, performed by the analysis of their models, is often
recommended to assess the correctness of safety-critical systems, failure of which could …

We present a SAT-based bounded model checking (BMC) method for timed interpreted
systems (TIS) and for properties expressible in the existential fragment of a Real-Time …

We present a new translation of Metric Temporal Logic with knowledge operators (MTLK) to
the Linear Temporal Logic with knowledge operators and with a new set of the atomic …