Integrated circuit structure with stepped epitaxial region
PH Suvarna, S Bentley, MV Raymond… - US Patent …, 2018 - Google Patents
Embodiments of the disclosure provide integrated circuit (IC) structures with stepped
epitaxial regions and methods of forming the same. A method according to the disclosure …
epitaxial regions and methods of forming the same. A method according to the disclosure …
Cross couple structure for vertical transistors
The disclosure provides integrated circuit (IC) structure including: a substrate; a shallow
trench isolation (STI) positioned between the first and second regions of the substrate; a first …
trench isolation (STI) positioned between the first and second regions of the substrate; a first …
Control of length in gate region during processing of VFET structures
Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a
fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the …
fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the …
Vertical-transport field-effect transistors having gate contacts located over the active region
R Xie, C Park, D Chanemougame, S Soss… - US Patent …, 2020 - Google Patents
Methods and structures that include a vertical-transport field-effect transistor. First and
second semiconductor fins are formed that project vertically from a bottom source/drain …
second semiconductor fins are formed that project vertically from a bottom source/drain …
Buried local interconnect in source/drain region
SJ Bentley, BC Paul, SR Soss - US Patent 10,418,368, 2019 - Google Patents
A method for forming a buried local interconnect in a source/drain region is disclosed
including, among other things, forming a plurality of VOC structures, forming a first …
including, among other things, forming a plurality of VOC structures, forming a first …
Integrated circuit devices including vertical field-effect transistors (VFETs)
JH Do - US Patent 11,056,489, 2021 - Google Patents
9,954,529 B2 4/2018 Anderson et al. 10,037,397 B2 7/2018 Moroz et al. 2017/0373071 Al
12/2017 Lim et al. 2018/0175024 A1 6/2018 Do et al. 2018/0197788 Al 7/2018 Anderson et …
12/2017 Lim et al. 2018/0175024 A1 6/2018 Do et al. 2018/0197788 Al 7/2018 Anderson et …
Memory devices and methods of manufacturing thereof
M Chang, C Huang, C Yi-Hsun, Y Wang - US Patent 10,971,505, 2021 - Google Patents
(57) ABSTRACT A memory cell is disclosed. The memory cell includes a first transistor. The
first transistor includes a first conduction channel collectively constituted by one or more first …
first transistor includes a first conduction channel collectively constituted by one or more first …
Buried local interconnect
K Cheng, LA Clevenger, C Radens, J Wang… - US Patent …, 2021 - Google Patents
2019-07-15 Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …
Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows
BA Anderson, SA Sieg, J Wang - US Patent 10,734,372, 2020 - Google Patents
(57) ABSTRACT A semiconductor structure includes a vertical transport static random-
access memory (SRAM) cell having a first active region and a second active region. The first …
access memory (SRAM) cell having a first active region and a second active region. The first …
Methods for VFET cell placement and cell architecture
(57) ABSTRACT A cell architecture and a method for placing a plurality of cells to form the
cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell …
cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell …