Analysis of the critical bits of a RISC-V processor implemented in an SRAM-based FPGA for space applications
One of the traditional issues in space missions is the reliability of the electronic components
on board spacecraft. There are numerous techniques to deal with this, from shielding and …
on board spacecraft. There are numerous techniques to deal with this, from shielding and …
Survivability modeling and resource planning for self-repairing reconfigurable device fabrics
RS Oreifej, R Al-Haddad, R Zand… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
A resilient system design problem is formulated as the quantification of uncommitted
reconfigurable resources required for a system of components to survive its lifetime within …
reconfigurable resources required for a system of components to survive its lifetime within …
Circuit level modeling of extra combinational delays in SRAM-based FPGAs due to transient ionizing radiation
M Darvishi, Y Audet, Y Blaquiere… - … on Nuclear Science, 2014 - ieeexplore.ieee.org
This paper presents circuit level models that explain the extra combinational delays in a
SRAM-based FPGA (Virtex-5) due to Single Event Upsets (SEUs). Several scenarios of extra …
SRAM-based FPGA (Virtex-5) due to Single Event Upsets (SEUs). Several scenarios of extra …
A fault-tolerant method of SRAM FPGA based on processor scrubbing
X Li, H Lou, Z Jin - 2021 IEEE 5th Advanced Information …, 2021 - ieeexplore.ieee.org
In order to improve the reliability of FPGA in space applications, a method of single event
upset detection and scrubbing based on internal processor is proposed for Xilinx Zynq …
upset detection and scrubbing based on internal processor is proposed for Xilinx Zynq …
Characterization of Interconnect Fault Effects in SRAM-based FPGAs
The configurable interconnect of SRAM-based FPGAs makes up a significant portion of their
configuration, and thus exposes a large attack surface to single-event upsets. A better …
configuration, and thus exposes a large attack surface to single-event upsets. A better …
SEE vulnerability bit analysis method for switch matrix of SRAM-based FPGA circuits
H Wei, W Yueke, X Kefei, D Wei - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
Analytical method is becoming a novel and attractive method to evaluate the Single Event
Effect (SEE) performance of the circuit implemented in SRAM-based FPGA. A SEE …
Effect (SEE) performance of the circuit implemented in SRAM-based FPGA. A SEE …
[图书][B] Characterization of Interconnection Delays in FPGAs Due to Single Event Upsets and Mitigation
M Darvishi - 2018 - search.proquest.com
The unrelenting demand for electronic components with ever diminishing feature size have
emerged new challenges over the years. Among them, more advanced memory and …
emerged new challenges over the years. Among them, more advanced memory and …
[PDF][PDF] Plataforma para testes e qualificação de dispositivos reconfiguráveis e sistemas em chip, submetidos aos efeitos combinados da interferência eletromagnética …
JD BENFICA - 2015 - core.ac.uk
Plataforma para Testes e Qualificação de Dispositivos Reconfiguráveis e Sistemas em Chip,
Submetidos aos Efeitos Combinados d Page 1 Juliano D’Ornelas Benfica Plataforma para Testes …
Submetidos aos Efeitos Combinados d Page 1 Juliano D’Ornelas Benfica Plataforma para Testes …