Saving power by mapping finite-state machines into embedded memory blocks in FPGAs
A Tiwari, KA Tomko - … design, automation and test in Europe …, 2004 - ieeexplore.ieee.org
Modern FPGAs contain on-chip synchronous embedded memory blocks (SEMBs), these
memory blocks can be used to implement control units, when not used as on-chip memory …
memory blocks can be used to implement control units, when not used as on-chip memory …
Low power finite state machine synthesis using power-gating
SN Pradhan, MT Kumar, S Chattopadhyay - Integration, 2011 - Elsevier
Power-gating turns off the power supply of a portion of the circuit completely, resulting in
total elimination of power consumption for that part. However, it also necessitates that the …
total elimination of power consumption for that part. However, it also necessitates that the …
Fuzzy c-mean clustering-based decomposition with GA optimizer for FSM synthesis targeting to low power
Y Tao, Y Zhang, Q Wang - Engineering Applications of Artificial Intelligence, 2018 - Elsevier
Reduction on both switching and leakage power has become a research focus in VLSI
design. It makes sense that finite-state machine (FSM) as a main component can contribute …
design. It makes sense that finite-state machine (FSM) as a main component can contribute …
SYSTEM, METHOD, AND PROGRAM FOR GENERATING NON-DETERMINISTIC FINITE AUTOMATON NOT INCLUDING e-TRANSITION
N Yamagaki - US Patent App. 12/452,987, 2010 - Google Patents
An initial setting unit receives from an input device a syntax tree generated from a regular
expression, and initializes an NFA and an NFA converting section that applies five …
expression, and initializes an NFA and an NFA converting section that applies five …
[HTML][HTML] Experiments in low power FPGA design
This paper summarizes the utility of some low-power design (LPD) methods based on
architectural and implementation modifications, for FPGA based systems. Power …
architectural and implementation modifications, for FPGA based systems. Power …
Power-driven design partitioning
R Mukherjee, SO Memik - … Conference on Field Programmable Logic and …, 2004 - Springer
In order to enable efficient integration of FPGAs into cost effective and reliable high-
performance systems as well potentially into low power mobile systems, their power …
performance systems as well potentially into low power mobile systems, their power …
Static power reduction in nano cmos circuits through an adequate circuit synthesis
L Jozwiak, D Gawlowski, A Slusarczyk… - … Conference on Mixed …, 2007 - ieeexplore.ieee.org
This paper addresses the power reduction issues in nano CMOS circuits, and focuses on the
static-power and power-efficient circuit synthesis. It shows that the circuit synthesis …
static-power and power-efficient circuit synthesis. It shows that the circuit synthesis …
Synthesis of clock gated circuit
M Jensen, A Goodrich, V Fouron - US Patent 9,003,339, 2015 - Google Patents
Technology for synthesizing a behavioral description of a circuit into a structural description
of the circuit is disclosed. The behavioral description may describe the circuit in terms of the …
of the circuit is disclosed. The behavioral description may describe the circuit in terms of the …
Genetic Fuzzy c-mean clustering-based decomposition for low power FSM synthesis
Y Tao, Q Wang, Y Zhang - 2017 IEEE Congress on …, 2017 - ieeexplore.ieee.org
Most published results show that power reduction of the finite-state machines (FSMs) is
achieved by decomposition. In order to achieve a low power FSM implementation, a Genetic …
achieved by decomposition. In order to achieve a low power FSM implementation, a Genetic …
[图书][B] Efficient Runtime Management of Reconfigurable Hardware Resources.
T Marconi - 2011 - researchgate.net
Runtime reconfigurable systems built upon devices with partial recon-figuration can provide
reduction in overall hardware area, power efficiency, and economic cost in addition to the …
reduction in overall hardware area, power efficiency, and economic cost in addition to the …