Floating gate memory device with interpoly charge trapping structure
HT Lue - US Patent 8,068,370, 2011 - Google Patents
(51) Int. Cl. A charge trapping floating gate is described with asymmetric GIC I6/06(2006.01)
tunneling barriers. The memory cell includes a source region HOIL 29/788(2006.01) and a …
tunneling barriers. The memory cell includes a source region HOIL 29/788(2006.01) and a …
Methods of operating p-channel non-volatile memory devices
HT Lue - US Patent 7,636,257, 2009 - Google Patents
Methods of operating non-volatile memory devices are described. The memory devices
comprise memory cells having an n-type semiconductor substrate and p-type source and …
comprise memory cells having an n-type semiconductor substrate and p-type source and …
Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
HT Lue, SY Wang - US Patent 8,264,028, 2012 - Google Patents
Memory cells comprising: a semiconductor substrate having a source region and a drain
region disposed below a surface of the substrate and separated by a channel region; a …
region disposed below a surface of the substrate and separated by a channel region; a …
Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
SY Wang, HT Lue - US Patent 7,642,585, 2010 - Google Patents
Memory cells comprising: a semiconductor substrate having a source region and a drain
region disposed below a surface of the substrate and separated by a channel region; a …
region disposed below a surface of the substrate and separated by a channel region; a …
Charge trapping memory cell with high speed erase
HT Lue, SC Lai - US Patent App. 11/845,276, 2009 - Google Patents
US20090039414A1 - Charge trapping memory cell with high speed erase - Google Patents
US20090039414A1 - Charge trapping memory cell with high speed erase - Google Patents …
US20090039414A1 - Charge trapping memory cell with high speed erase - Google Patents …
Method of forming non-volatile memory having charge trap layer with compositional gradient
M Balseanu, V Zubkov, LQ Xia, A Noori… - US Patent …, 2010 - Google Patents
(57) ABSTRACT A flash memory device and method of forming a flash memory device are
provided. The flash memory device includes a silicon nitride layer having a compositional …
provided. The flash memory device includes a silicon nitride layer having a compositional …
Structure and method of sub-gate NAND memory with bandgap engineered SONOS devices
HT Lue, HM Lien - US Patent 7,948,799, 2011 - Google Patents
A bandgap engineered SONOS device structure for design with various AND architectures.
The BE-SONOS device structure comprises a spacer oxide disposed between a control gate …
The BE-SONOS device structure comprises a spacer oxide disposed between a control gate …
High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
SC Lai, HT Lue, CW Liao - US Patent 7,816,727, 2010 - Google Patents
3/2007 Shih et al. 4,630,086 A 12/1986 Sato et al. 2007, 0120179 A1 5, 2007 Park et al.
5,286,994 A 2f1994 Ozawa et al. 2007, 0138539 A1 6, 2007 Wu et al. 5,319,229 A 6/1994 …
5,286,994 A 2f1994 Ozawa et al. 2007, 0138539 A1 6, 2007 Wu et al. 5,319,229 A 6/1994 …
Blocking dielectric engineered charge trapping memory cell with high speed erase
SC Lai, HT Lue, CW Liao - US Patent 7,737,488, 2010 - Google Patents
US PATENT DOCUMENTS 6,885,044 B2 4/2005 Ding 6,888,750 B2 5/2005 Walker et al.
5,515,324 A 5, 1996 Tanaka et al. 6,897,533 B1 5/2005 Yang et al. 5,602,775 A 2, 1997 Vo …
5,515,324 A 5, 1996 Tanaka et al. 6,897,533 B1 5/2005 Yang et al. 5,602,775 A 2, 1997 Vo …
Silicon on insulator and thin film transistor bandgap engineered split gate memory
Jan. 3, 2006, now Pat. No. 7,315,474, application No.(74) Attorney, Agent, or Firm—
McClure, Qualey & 12/056,489, which is a continuation-in-part of Rodack, LLP application …
McClure, Qualey & 12/056,489, which is a continuation-in-part of Rodack, LLP application …