The design of scalar AES instruction set extensions for RISC-V

B Marshall, GR Newell, D Page… - IACR …, 2021 - moving-the-social.ub.rub.de
Secure, efficient execution of AES is an essential requirement on most computing platforms.
Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a …

Security evaluation of DPA countermeasures using dual-rail pre-charge logic style

D Suzuki, M Saeki - … on Cryptographic Hardware and Embedded Systems, 2006 - Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the
logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a …

Instruction set extensions for efficient AES implementation on 32-bit processors

S Tillich, J Großschädl - … Hardware and Embedded Systems-CHES 2006 …, 2006 - Springer
Secure communication over public networks like the Internet requires the use of
cryptographic algorithms as basic building blocks. Most cryptographic workloads pose a …

Flexible architecture and instruction for advanced encryption standard (AES)

S Gueron, WK Feghali, V Gopal… - US Patent …, 2013 - Google Patents
A flexible instruction set for a general purpose processor is provided. The instruction set
includes instructions to perform a “one round” pass for encryption or decryption and also …

Cryptoraptor: High throughput reconfigurable cryptographic processor

G Sayilar, D Chiou - 2014 IEEE/ACM International Conference …, 2014 - ieeexplore.ieee.org
This paper describes a high performance, low power, and highly flexible cryptographic
processor, Cryptoraptor, which is designed to support both today's and tomorrow's …

SoK: Instruction Set Extensions for Cryptographers

H Cheng, J Großschädl, B Marshall, D Page… - Cryptology ePrint …, 2024 - eprint.iacr.org
Framed within the general context of cyber-security, standard cryptographic constructions
often represent an enabling technology for associated solutions. Alongside or in …

Power analysis resistant AES implementation with instruction set extensions

S Tillich, J Großschädl - … Hardware and Embedded Systems-CHES 2007 …, 2007 - Springer
In recent years, different instruction set extensions for cryptography have been proposed for
integration into general-purpose RISC processors. Both public-key and secret-key …

Light-weight instruction set extensions for bit-sliced cryptography

P Grabher, J Großschädl, D Page - … , Washington, DC, USA, August 10-13 …, 2008 - Springer
Bit-slicing is a non-conventional implementation technique for cryptographic software where
an n-bit processor is considered as a collection of n 1-bit execution units operating in SIMD …

Efficient hashing using the AES instruction set

JW Bos, O Özen, M Stam - International Workshop on Cryptographic …, 2011 - Springer
In this work, we provide a software benchmark for a large range of 256-bit blockcipher-
based hash functions. We instantiate the underlying blockcipher with AES, which allows us …

Boosting AES performance on a tiny processor core

S Tillich, C Herbst - Cryptographers' Track at the RSA Conference, 2008 - Springer
Notwithstanding the tremendous increase in performance of desktop computers, more and
more computational work is performed on small embedded microprocessors. Particularly …