Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate …

S Senthilkumar, V Samuthira Pandi… - Concurrency and …, 2023 - Wiley Online Library
Recustomize finite impulse response (RFIR) filter is designed to achieve lesser power
consume, cost, area, and higher speed of system operation. This is used to remove the …

Current‐Fed Bidirectional DC‐DC Converter Topology for Wireless Charging System Electrical Vehicle Applications

PS Subudhi, M Thilagaraj… - Wireless …, 2021 - Wiley Online Library
This paper compares the efficiency of a modified wireless power transfer (WPT) system with
a current‐fed dual‐active half‐bridge converter topology and a complete bridge converter …

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image …

P Mahendran, MS Kavitha, R Radhika… - Concurrency and …, 2023 - Wiley Online Library
A design of all pass make over based capricious digital filter using eminent speed dual carry
select adder and truncation based scalable rounding approximate multiplier (APM‐CDF …

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography

S Janwadkar, R Dhavse - Microprocessors and Microsystems, 2024 - Elsevier
Impedance cardiography (ICG) is a rapidly growing non-invasive cardiac health monitoring
approach. Synchronous detection of ICG requires an FIR filter to remove the high-frequency …

Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal …

K Saritha Raj, P Rajesh Kumar… - Circuits, Systems, and …, 2023 - Springer
Capricious digital filter (CDF) plays a significant role of signal processing application field to
eradicate noise. Any prototype filter desired frequency response is attained by developing …

Strategic reduction of area and power in FIR filter architecture for ECG signal acquisition

S Janwadkar, R Dhavse - 2020 IEEE 17th India Council …, 2020 - ieeexplore.ieee.org
Literature on VLSI implementation of Finite Impulse Response (FIR) filters has scarce
mention of dedicated filters for portable Electrocardiogram (ECG) acquisition system …

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

S Janwadkar, R Dhavse - International Journal of Circuit Theory …, 2024 - Wiley Online Library
The design of hand‐held portable devices for cardiovascular health monitoring based on the
analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters …

XOR-Free Approach Towards Realization of Low Pass FIR Filter in Bio-Medical Signal Acquisition: Vedic Multiplier-based ASIC Implementation

S Janwadkar, R Dhavse - 2023 IEEE 20th India Council …, 2023 - ieeexplore.ieee.org
FIR filters implementations using digital adders and multipliers frequently use power-hungry
XOR gate-based combinational logic circuits. Through this paper, we propose a novel …

Carry Select Adder Using Square Root Techniques in Ripple Carry and BCD Adders

R Subramanyam, VAK Talluri… - 2024 IEEE 13th …, 2024 - ieeexplore.ieee.org
Carry select adder (CSA) finds application in increasing the speed of additions in various
processing units. However, the design of this CSA is a challenge because the gates used in …

[PDF][PDF] High Performance Reversible Vedic Multiplier Using Cadence 45nm Technology

S Prema, SV Ramanan, RA Sekar… - International Journal of …, 2019 - researchgate.net
Vedic science is an antiquated strategy of Indian arithmetic as it contains 16 Sutras. A fast
16* 16 multiplier configuration is designed utilizing Urdhva Tiryakbhyam sutra is introduced …