An optimized modified booth recoder for efficient design of the add-multiply operator

K Tsoumanis, S Xydis, C Efstathiou… - … on Circuits and …, 2014 - ieeexplore.ieee.org
Complex arithmetic operations are widely used in Digital Signal Processing (DSP)
applications. In this work, we focus on optimizing the design of the fused Add-Multiply (FAM) …

A framework for hardware trojan vulnerability estimation and localization in RTL designs

SA Islam, LK Sah, S Katkoori - Journal of Hardware and Systems Security, 2020 - Springer
As the design complexity increases, the attack space for malicious modifications in the
design also increases. Attackers in untrusted phases during the Integrated Circuit (IC) …

[HTML][HTML] A new clock gated flip flop for pipelining architecture

K Raja, S Saravanan - Circuits and Systems, 2016 - scirp.org
The objective of the work is to design a new clock gated based flip flop for pipelining
architecture. In computing and consumer products, the major dynamic power is consumed in …

Power estimation of modified booth recoder for efficient add-multiply operator

K Shruthilaya, M Vinoth - 2015 2nd International Conference …, 2015 - ieeexplore.ieee.org
To improve the performance and speed of Digital signal processing operations such as FFT
(Fast Fourier Transform), DCT (Discrete Cosine Transform) and FIR (Finite Impulse …

Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs

SA Islam, LK Sah, S Katkoori - 2020 21st International …, 2020 - ieeexplore.ieee.org
Offshoring the proprietary Intellectual property (IP) has recently increased the threat of
malicious logic insertion in the form of Hardware Trojan (HT). A potential and stealthy HT is …

Low latency prefix accumulation driven compound MAC unit for efficient FIR filter implementation

GR Hemantha, S Varadarajan… - Journal of Scientific & …, 2022 - op.niscpr.res.in
This article presents hierarchical single compound adder-based MAC with assertion based
error correction for speculation variations in the prefix addition for FIR filter design. The VLSI …

An efficient modified Booth recoder for different applications

VM Bai, M Sailaja - 2016 International Conference on …, 2016 - ieeexplore.ieee.org
In Dsp applications complex arithmetic operations are performed. In order to improve the
performances of Dsp applications we focus on optomizing the design of fused add multiply …

[PDF][PDF] AN IMPLEMENTATION OF AREA EFFICIENT & FAST ADDITION AND MULTIPLICATION OPERATION USING RADIX BASED MODIFIED BOOTH RECODING …

TL Kumar, N Shehanaz - ijetcse.com
& Multiplication operation using Radix based Modified Booth Technique and then also it is
implemented. The Modified Booth Recoding Technique is mainly used to produce the …

Behavioral and RT-Level Synthesis of Secure Nano VLSI Digital ASIC Designs

SA Islam - 2020 - search.proquest.com
The proliferation of embedded systems in our daily lives, including national interests, is
largely backed by the success of the nanometer scale Integrated Circuit (IC). The increasing …

[PDF][PDF] An Optimised Add Multiply Operator Using S-MB

SK MM - academia.edu
Optimizing the fused add multiply (FAM) operator increase the performance of Digital Signal
Processing (DSP) Applications. This paper proposes the design and development of FAM …