Machine learning-based hotspot detection: Fallacies, pitfalls and marching orders

GR Reddy, K Madkour, Y Makris - 2019 IEEE/ACM International …, 2019 - ieeexplore.ieee.org
Extensive technology scaling has not only increased the complexity of Integrated Circuit (IC)
fabrication but also multiplied the challenges in the Design For Manufacturability (DFM) …

To DFM or not to DFM?

WC Tam, S Blanton - Proceedings of the 48th Design Automation …, 2011 - dl.acm.org
Design for manufacturability (DFM) is inevitable because of the formidable challenges
encountered in nano-scale integrated circuit (IC) manufacturing. Unfortunately, it is difficult …

Physically-aware analysis of systematic defects in integrated circuits

WC Tam, RD Blanton - 2011 IEEE International Test …, 2011 - ieeexplore.ieee.org
Systematic defects due to design-process interactions are a significant component of
integrated circuit (IC) yield loss in nano-scale technologies. Test structures do not …

Design-for-manufacturability assessment for integrated circuits using radar

WC Tam, S Blanton - … on Computer-Aided Design of Integrated …, 2014 - ieeexplore.ieee.org
Design for manufacturability (DFM) is essential because of the formidable challenges
encountered in nano-scale integrated circuit (IC) fabrication. Unfortunately, it is difficult for …

Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve

I Pomeranz - IEEE Transactions on Very Large Scale …, 2024 - ieeexplore.ieee.org
The fabrication processes of chips in state-of-the-art technologies may introduce defects of
various types, and a large number of tests may be needed for fault detection. However …

Resynthesis for avoiding undetectable faults based on design-for-manufacturability guidelines

N Wang, I Pomeranz, SM Reddy… - … , Automation & Test …, 2019 - ieeexplore.ieee.org
As integrated circuit manufacturing advances, the occurrence of systematic defects is
expected to be prominent. A methodology for predicting potential systematic defects based …

Pattern matching rule ranking through design of experiments and silicon validation

G Rajavendra Reddy, J Wallner… - … for Testing and …, 2018 - dl.asminternational.org
Continued technology scaling has led to exposure of many 'weak-points' in the designs
fabricated in some of the most advanced technology nodes. Weak-points are certain layout …

Layout resynthesis by applying design-for-manufacturability guidelines to avoid low-coverage areas of a cell-based design

N Wang, I Pomeranz, SM Reddy, A Sinha… - ACM Transactions on …, 2019 - dl.acm.org
Design-for-manufacturability (DFM) guidelines are recommended layout design practices
intended to capture layout features that are difficult to manufacture correctly. Avoiding such …

Improving Coverage of Circuits by Using Different Fault Models Complementing Each Other

O Basu - 2021 - search.proquest.com
Various fault models such as stuck-at, transition, bridging have been developed to better
model possible defects in manufactured chips. However, over the years as device sizes …

Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching Orders

G Rajavendra Reddy - 2020 - utd-ir.tdl.org
Extensive technology scaling has not only increased the complexity of Integrated Circuit (IC)
fabrication but also multiplied the challenges in the Design For Manufacturability (DFM) …