We present a 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/of die area, dissipates 90 mW of
power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS …

A 4.9-6.4-Gb/s two-level SerDes ASIC I/O core employing a four-tap feed-forward equalizer
(FFE) in the transmitter and a five-tap decision-feedback equalizer (DFE) in the receiver has …

Clock recovery using phase-locked loops (PLL) with binary (bang-bang) or ternary-
quantized phase detectors has become increasingly common starting with the advent of fully …

The application of adaptive power-supply regulation is extended to serial links. The adaptive
supply maximizes the energy-efficiency of the I/O circuits and serves as a global bias to …

A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate
topology with purely digital blocks to substantially reduce power consumption. The receiver …

This paper describes the design and implementation of a quad high-speed transceiver cell
fabricated in 0.13-μm CMOS technology. The clocking circuit of the cell employs a dual-loop …

In this tutorial paper we present equalization techniques to mitigate inter-symbol interference
(ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed …

This document describes and discloses a set of ideas for improving the bandwidth on a
signaling system composed of more than one wire. These ideas represent a generalization …

This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval
3/spl times/-oversampling method for enhanced high-frequency jitter tolerance. The CDR …

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver
using a standard CMOS process. Careful design methodology combined with a standard …