IPP@ HDL: Efficient intellectual property protection scheme for IP cores
In this paper, a procedure for intellectual property protection (IPP) of digital circuits called
IPP@ HDL is presented. Its aim is to protect the author rights in the development and …
IPP@ HDL is presented. Its aim is to protect the author rights in the development and …
On modulo 2^ n+ 1 adder design
HT Vergos, G Dimitrakopoulos - IEEE transactions on …, 2010 - ieeexplore.ieee.org
Two architectures for modulo 2 n+ 1 adders are introduced in this paper. The first one is built
around a sparse carry computation unit that computes only some of the carries of the modulo …
around a sparse carry computation unit that computes only some of the carries of the modulo …
RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to -bit
In the last years, investigation on residue number systems (RNS) has targeted parallelism
and larger dynamic ranges. In this paper, we start from the moduli set {2 n, 2 n-1, 2 n+ 1, 2 n …
and larger dynamic ranges. In this paper, we start from the moduli set {2 n, 2 n-1, 2 n+ 1, 2 n …
Design of efficient modulo 2n+ 1 multipliers
HT Vergos, C Efstathiou - IET Computers & Digital Techniques, 2007 - IET
A new modulo 2n+ 1 multiplier architecture is proposed for operands in the weighted
representation. A new set of partial products is derived and it is shown that all required …
representation. A new set of partial products is derived and it is shown that all required …
A Unifying Approach for Weighted and Diminished-1 Modulo Addition
HT Vergos, C Efstathiou - … on Circuits and Systems II: Express …, 2008 - ieeexplore.ieee.org
In this paper, it is shown that every architecture proposed for modulo 2 n+ 1 addition of
operands that follow the diminished-1 representation can also be used in the design of …
operands that follow the diminished-1 representation can also be used in the design of …
RNS processor using moduli sets of the form 2n±1
V Prediger, F Bairros, LO Seman… - … Journal of Circuit …, 2023 - Wiley Online Library
In recent years, research on residue number systems (RNS) has targeted larger dynamic
ranges to explore their inherent parallelism further. In this paper, we start from the traditional …
ranges to explore their inherent parallelism further. In this paper, we start from the traditional …
Efficient modulo 2n+ 1 adder architectures
HT Vergos, C Efstathiou - Integration, 2009 - Elsevier
In this manuscript, we introduce novel carry lookahead (CLA) and parallel-prefix
architectures for the design of modulo 2n+ 1 adders with operands in the diminished-1 …
architectures for the design of modulo 2n+ 1 adders with operands in the diminished-1 …
On the Design of Modulo 2 n ±1 Subtractors and Adders/Subtractors
Novel architectures for designing modulo 2 n+ 1 subtractors and combined
adders/subtractors are proposed in this manuscript. Both the normal and the diminished-one …
adders/subtractors are proposed in this manuscript. Both the normal and the diminished-one …
Diminished-1 modulo 2n+ 1 squarer design
HT Vergos, C Efstathiou - IEE Proceedings-Computers and Digital Techniques, 2005 - IET
Squarers modulo M are useful design blocks for digital signal processors that internally use
a residue number system and for implementing the exponentiators required in cryptographic …
a residue number system and for implementing the exponentiators required in cryptographic …
Fast modulo 2n+ 1 multi-operand adders and residue generators
In this manuscript novel architectures for modulo 2n+ 1 multi-operand addition and residue
generation are introduced. The proposed arithmetic components consist of a translation …
generation are introduced. The proposed arithmetic components consist of a translation …