The ever-increasing functionality of modern electronic systems and reduced time-to-market
constraints have significantly altered the typical design flow. One possible solution to deal …

The exponential increase in functionality of System-on-Chips (SoCs) and reduced Time-to-
Market (TTM) requirements have significantly altered the typical design and verification flow …

For effective embedded system design, transaction level modeling (TLM) must explicitly
expose any available parallelism in the application. Traditional TLM in SystemC utilizes …

The emergence of data-intensive applications, such as Deep Neural Networks (DNNs),
exacerbates the well-known memory bottleneck in computer systems and demands early …

The IEEE SystemC standard is widely used to specify and simulate Electronic System Level
(ESL) design models. Despite the wide availability of multi-core processor hosts, however …

We present SCCL, an open-source tool that translates SystemC designs into synthesizable
register-transfer level (RTL). SCCL supports a subset of Accellera's SystemC synthesis …

The complexity of hardware designs is still increasing according to Moore's law. With
embedded systems being more and more intertwined and working together not only with …

In an ideal top-down system design flow, graphical diagrams are designed before an
executable specification in a System Level Description Language (SLDL) is derived. Such …

The emergence of virtual prototypes (VPs) at the electronic system level (ESL) has played a
major role in modernizing the system-on-chips (SoCs) design process to raise design …

Within this paper an adaptive approach for parallel simulation of SystemC RTL models on
future many-core architectures like the Single-chip Cloud Computer (SCC) from Intel is …