Study of various high speed multipliers

S Abraham, S Kaur, S Singh - 2015 International Conference …, 2015 - ieeexplore.ieee.org
Multiplication or repeated addition is the basic operation used in both Mathematics and
Science. The speed of multiplier determines the speed of all Digital Signal Processors. This …

Design and implementation of fast floating point multiplier unit

NV Sunesh, P Sathishkumar - 2015 International Conference …, 2015 - ieeexplore.ieee.org
Floating point numbers are the quantities that cannot be represented by integers, either
because they contain fractional values or because they lie outside the range re presentable …

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

S Arish, RK Sharma - 2015 international conference on signal …, 2015 - ieeexplore.ieee.org
Floating point multiplication is a crucial operation in high power computing applications such
as image processing, signal processing etc. And also multiplication is the most time and …

Design and performance comparison of adiabatic 8-bit multipliers

HVR Aradhya, HR Madan, MS Suraj… - 2016 IEEE …, 2016 - ieeexplore.ieee.org
The advancement of transistor process technology reduces chip area at the cost of the total
power consumption. Adiabatic logic, one of the promising low power techniques in VLSI …

Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications

S Arish, RK Sharma - 2015 2nd International Conference on …, 2015 - ieeexplore.ieee.org
Floating point multiplication is one of the crucial operations in many application domains
such as image processing, signal processing etc. But every application requires different …

FPGA based implementation of a floating point multiplier and its hardware trojan models

S Nikhila, B Yamuna… - 2019 IEEE 16th India …, 2019 - ieeexplore.ieee.org
Floating point multiplication plays a crucial role in computationally intensive applications like
digital signal processing. This paper deals with the design of a single precision floating point …

Design and verification of dadda algorithm based binary floating point multiplier

V Buddhe, P Palsodkar… - … on Communication and …, 2014 - ieeexplore.ieee.org
This paper presents a fast single precision floating point multiplier. In most of the industrial
areas like DSP, image processing, microprocessor, it is needed to do arithmetic operations …

Run-time-reconfigurable multi-precision floating-point matrix multiplier intellectual property core on FPGA

S Arish, RK Sharma - Circuits, Systems, and Signal Processing, 2017 - Springer
In today's world, high-power computing applications such as image processing, digital
signal processing, graphics, robotics require enormous computing power. These …

[PDF][PDF] VLSI implementation of neural network

JR Shinde, S Salankar - Current Trends in Technology and Science, 2015 - academia.edu
This paper proposes a novel approach for an optimal multi-objective optimization for VLSI
implementation of Artificial Neural Network (ANN) which is area-power-speed efficient and …

VLSI implementation of bit serial architecture based multiplier in floating point arithmetic

JR Shinde, SS Salankar - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
VLSI implementation of Neural network processing or digital signal processing based
applications comprises large number of multiplication operations. A key design issue …