Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors
WM Weber, T Mikolajick - Reports on Progress in Physics, 2017 - iopscience.iop.org
Research in the field of electronics of 1D group-IV semiconductor structures has attracted
increasing attention over the past 15 years. The exceptional combination of the unique 1D …
increasing attention over the past 15 years. The exceptional combination of the unique 1D …
A comprehensive compact model for GaN HEMTs, including quasi-steady-state and transient trap-charge effects
B Syamal, X Zhou, SB Chiah… - … on Electron Devices, 2016 - ieeexplore.ieee.org
A comprehensive scalable trap-charge model for the dc and pulsed IV modeling of GaN high
electron-mobility transistor is presented. While interface traps are considered for dc IV …
electron-mobility transistor is presented. While interface traps are considered for dc IV …
Performance and variations induced by single interface trap of nanowire FETs at 7-nm node
DC/AC performance and the variations due to single interface trap of the nanowire (NW)
FETs were investigated in the 7-nm technology node using fully calibrated TCAD simulation …
FETs were investigated in the 7-nm technology node using fully calibrated TCAD simulation …
Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering
The aim of this study is to investigate the memory performances of gate-all-around floating
gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable …
gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable …
A novel charge pumping technique with gate-induced drain leakage current
GB Lee, JY Kim, YK Choi - IEEE Electron Device Letters, 2023 - ieeexplore.ieee.org
A charge pumping (CP) technique with gate-induced drain leakage (GIDL) current is
proposed to extract interface trap density (in GAA MOSFETs. This GIDL CP characterizes the …
proposed to extract interface trap density (in GAA MOSFETs. This GIDL CP characterizes the …
Analytical current–voltage modeling and analysis of the MFIS gate-all-around transistor featuring negative-capacitance
Y Kim, Y Seon, S Kim, J Kim, S Bae, I Yang, C Yoo… - Electronics, 2021 - mdpi.com
Recently, in accordance with the demand for development of low-power semiconductor
devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric …
devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric …
Noise Spectroscopy Analysis of Ion Behavior in Liquid Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors
Y Zhang, N Boichuk, D Pustovyi… - Advanced Materials …, 2023 - Wiley Online Library
The transport and noise properties of fabricated, high‐performance, gate‐all‐around silicon
liquid‐gated nanowire field‐effect transistor devices are investigated in different …
liquid‐gated nanowire field‐effect transistor devices are investigated in different …
Two-dimensional (2D) transition metal dichalcogenide semiconductor field-effect transistors: the interface trap density extraction and compact model
A surface potential-based low-field drain current compact model is presented for two-
dimensional (2D) transition metal dichalcogenide (TMD) semiconductor field-effect …
dimensional (2D) transition metal dichalcogenide (TMD) semiconductor field-effect …
Extraction of interface trap density through synchronized optical charge pumping in gate-all-around MOSFETs
GB Lee, YK Choi - IEEE Electron Device Letters, 2020 - ieeexplore.ieee.org
The number of interface traps (N it) in a gate-all-around (GAA) MOSFET that harnesses an
inherent floating body, was analyzed by using the synchronized optical charge pumping …
inherent floating body, was analyzed by using the synchronized optical charge pumping …
Floating gate potential of gate-all-around floating gate memory cell: parameter extraction and compact model
The compact modeling of flash memories is crucial for integrated circuit designers to carry
out efficient and precise circuit-level evaluations, particularly in the case of 3D NAND flash …
out efficient and precise circuit-level evaluations, particularly in the case of 3D NAND flash …