Survey of turbo, LDPC, and polar decoder ASIC implementations
S Shao, P Hailes, TY Wang, JY Wu… - … Surveys & Tutorials, 2019 - ieeexplore.ieee.org
Channel coding may be viewed as the best-informed and most potent component of cellular
communication systems, which is used for correcting the transmission errors inflicted by …
communication systems, which is used for correcting the transmission errors inflicted by …
An efficient combined bit-flipping and stochastic LDPC decoder using improved probability tracers
This paper presents an efficient combined bit-flipping (BF) and stochastic low-density parity-
check decoder, where a BF decoder is used to achieve a reduction in decoding cycles. A …
check decoder, where a BF decoder is used to achieve a reduction in decoding cycles. A …
A high-performance stochastic LDPC decoder architecture designed via correlation analysis
Q Zhang, Y Chen, S Li, X Zeng… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This paper presents an area-efficient architecture for stochastic low-density parity-check
(LDPC) decoder with high throughput and excellent bit-error-rate (BER) performance. The …
(LDPC) decoder with high throughput and excellent bit-error-rate (BER) performance. The …
A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory
Y Zhou, J Chen, Y Zhou, Z Xia… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
The complex calculations of the low-density parity-check (LDPC) decoder result in
significant energy and hardware consumption. To solve the challenge, this brief describes a …
significant energy and hardware consumption. To solve the challenge, this brief describes a …
Design and implementation of flexible FPGA-based LDPC decoders
P Hailes - 2018 - eprints.soton.ac.uk
Since their rediscovery in the mid-1990s, Low-Density Parity Check (LDPC) error correction
decoders have been the focus of a great deal of research within the communications …
decoders have been the focus of a great deal of research within the communications …
A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm
A fully-parallel high-throughput LDPC decoder architecture leads to high power
consumption and large area. Using stochastic logic, this paper proposes three novel …
consumption and large area. Using stochastic logic, this paper proposes three novel …
Convergence-optimized variable node structure for stochastic LDPC decoder
By using stochastic computation, a fully-parallel low-density parity-check (LDPC) decoder
can be implemented using a lower wire complexity. In order to enhance the decoder …
can be implemented using a lower wire complexity. In order to enhance the decoder …