BACKGROUND An all-digital phase locked loop (ADPLL) is a circuit that locks the phase of
a local oscillator clock signal, output from the ADPLL, to the phase of a frequency reference …

Some embodiments include apparatuses and methods of operating such apparatuses. One
of the apparatuses includes a first circuit included in a phase-locked loop (PLL) to receive an …

(57) ABSTRACT Related US Application Data A fractional-N divider of a frequency
synthesizer is driven by (60) Provisional application No. 61/867,759, filed on Aug. a dither …

(57) ABSTRACT A fractional-N divider of a frequency synthesizer is driven by a dither-less
error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train …

(57) ABSTRACT A fractional-N divider of a frequency synthesizer is driven by a dither-less
error feedback modulator to alleviate frac tional spurious tones introduced by the cyclic train …

Disclosed herein is a device that includes a coarse adjusting circuit generating first and
second clock signals having dif ferent phases from each other, and a fine adjusting circuit …

It has been found infractional-nphase locked loops (PLLs) when Switching from one
frequency represented by n to a second frequency represented by n+ 1, that the phase of the …

(57) ABSTRACT A fractional-N divider of a frequency synthesizer is driven by a dither-less
and seed-less multi-stage noise shaping (MASH) modulator to alleviate fractional spurious …

A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a
reference frequency signal and a feedback frequency signal and configured to output a …

An apparatus is described and includes a current integrating phase interpolator core having
a programmable bias current; an AC-coupled inverter circuit coupled to an output of the …